[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() fun
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-ppc] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() function |
Date: |
Thu, 7 Mar 2019 18:05:15 +0000 |
Instead of having multiple copies of the offset calculation logic, move it to a
single vsrl_offset() function.
This commit also renames the existing get_vsr()/set_vsr() functions to
get_vsrl()/set_vsrl() which better describes their purpose.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/cpu.h | 7 ++++++-
target/ppc/translate/vsx-impl.inc.c | 12 ++++++------
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4bb4e42670..4a7df13c2d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2573,9 +2573,14 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env,
int i)
return (uint64_t *)((uintptr_t)env + fpr_offset(i));
}
+static inline int vsrl_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[i].u64[1]);
+}
+
static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
{
- return &env->vsr[i].u64[1];
+ return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
}
static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index e73197e717..381ae0f2e9 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1,13 +1,13 @@
/*** VSX extension ***/
-static inline void get_vsr(TCGv_i64 dst, int n)
+static inline void get_vsrl(TCGv_i64 dst, int n)
{
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));
+ tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n));
}
-static inline void set_vsr(int n, TCGv_i64 src)
+static inline void set_vsrl(int n, TCGv_i64 src)
{
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));
+ tcg_gen_st_i64(src, cpu_env, vsrl_offset(n));
}
static inline int vsr_full_offset(int n)
@@ -27,7 +27,7 @@ static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
static inline void get_cpu_vsrl(TCGv_i64 dst, int n)
{
if (n < 32) {
- get_vsr(dst, n);
+ get_vsrl(dst, n);
} else {
get_avr64(dst, n - 32, false);
}
@@ -45,7 +45,7 @@ static inline void set_cpu_vsrh(int n, TCGv_i64 src)
static inline void set_cpu_vsrl(int n, TCGv_i64 src)
{
if (n < 32) {
- set_vsr(n, src);
+ set_vsrl(n, src);
} else {
set_avr64(n - 32, src, false);
}
--
2.11.0
- [Qemu-ppc] [PATCH v2 0/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal.h to cpu.h, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 6/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() function,
Mark Cave-Ayland <=
- [Qemu-ppc] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 1/7] target/ppc: introduce single fpr_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 4/7] target/ppc: introduce avr_full_offset() function, Mark Cave-Ayland, 2019/03/07
- [Qemu-ppc] [PATCH v2 7/7] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), Mark Cave-Ayland, 2019/03/07