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[Qemu-ppc] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interru
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interrupt types |
Date: |
Mon, 28 Jan 2019 10:46:24 +0100 |
From: Benjamin Herrenschmidt <address@hidden>
It should be generic Hypervisor Virtualization interrupts for HV
directed rings and traditional External Interrupts for the OS directed
ring.
Don't generate anything for the user ring as it isn't actually
supported.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/ppc/xive.h | 3 ++-
hw/intc/xive.c | 22 +++++++++++++++++++---
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 2bad8526221b..82e9aef677c5 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -316,7 +316,8 @@ typedef struct XiveTCTX {
DeviceState parent_obj;
CPUState *cs;
- qemu_irq output;
+ qemu_irq hv_output;
+ qemu_irq os_output;
uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
uint32_t hw_cam;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 119bb02d345d..14b854181ab7 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -61,13 +61,28 @@ static uint8_t exception_mask(uint8_t ring)
}
}
+static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring)
+{
+ switch (ring) {
+ case TM_QW0_USER:
+ return 0; /* Not supported */
+ case TM_QW1_OS:
+ return tctx->os_output;
+ case TM_QW2_HV_POOL:
+ case TM_QW3_HV_PHYS:
+ return tctx->hv_output;
+ default:
+ return 0;
+ }
+}
+
static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring)
{
uint8_t *regs = &tctx->regs[ring];
uint8_t nsr = regs[TM_NSR];
uint8_t mask = exception_mask(ring);
- qemu_irq_lower(tctx->output);
+ qemu_irq_lower(xive_tctx_output(tctx, ring));
if (regs[TM_NSR] & mask) {
uint8_t cppr = regs[TM_PIPR];
@@ -100,7 +115,7 @@ static void xive_tctx_notify(XiveTCTX *tctx, uint8_t ring)
default:
g_assert_not_reached();
}
- qemu_irq_raise(tctx->output);
+ qemu_irq_raise(xive_tctx_output(tctx, ring));
}
}
@@ -554,7 +569,8 @@ static void xive_tctx_realize(DeviceState *dev, Error
**errp)
env = &cpu->env;
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_POWER9:
- tctx->output = env->irq_inputs[POWER7_INPUT_INT];
+ tctx->hv_output = env->irq_inputs[POWER9_INPUT_HINT];
+ tctx->os_output = env->irq_inputs[POWER9_INPUT_INT];
break;
default:
--
2.20.1
- [Qemu-ppc] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg, (continued)
- [Qemu-ppc] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 05/19] ppc/pnv: add XIVE support, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 13/19] target/ppc: Rename "in_pm_state" to "resume_as_sreset", Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 14/19] target/ppc: Add POWER9 exception model, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 17/19] target/ppc: Add POWER9 external interrupt model, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 16/19] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 11/19] target/ppc: Move "wakeup reset" code to a separate function, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 12/19] target/ppc: Disable ISA 2.06 PM instructions on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWER9, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instructions, Cédric Le Goater, 2019/01/28
- [Qemu-ppc] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interrupt types,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH 15/19] target/ppc: Detect erroneous condition in interrupt delivery, Cédric Le Goater, 2019/01/28