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[Qemu-ppc] [PATCH 13/13] target/ppc: Implement the rest of gen_st_atomic
From: |
Richard Henderson |
Subject: |
[Qemu-ppc] [PATCH 13/13] target/ppc: Implement the rest of gen_st_atomic |
Date: |
Tue, 26 Jun 2018 09:19:21 -0700 |
The store twin case was stubbed out. For now, implement it only within
a serial context, forcing parallel execution to synchronize. It would
be possible to implement with a cmpxchg loop, if we care, but the loose
alignment requirements (simply no crossing 32-byte boundary) might send
us back to the serial context anyway.
Signed-off-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 597a37d3ec..e120f2ed0b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3254,7 +3254,31 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemOp
memop)
tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
break;
case 24: /* Store twin */
- gen_invalid(ctx);
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ /* Restart with exclusive lock. */
+ gen_helper_exit_atomic(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ } else {
+ TCGv t = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv s = tcg_temp_new();
+ TCGv s2 = tcg_temp_new();
+ TCGv ea_plus_s = tcg_temp_new();
+
+ tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
+ tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
+ tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
+ tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
+ tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
+ tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
+ tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
+
+ tcg_temp_free(ea_plus_s);
+ tcg_temp_free(s2);
+ tcg_temp_free(s);
+ tcg_temp_free(t2);
+ tcg_temp_free(t);
+ }
break;
default:
/* invoke data storage error handler */
--
2.17.1
- Re: [Qemu-ppc] [PATCH 01/13] target/ppc: Add do_unaligned_access hook, (continued)
- [Qemu-ppc] [PATCH 05/13] target/ppc: Remove POWERPC_EXCP_STCX, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 06/13] target/ppc: Tidy gen_conditional_store, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 07/13] target/ppc: Split out gen_load_locked, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 09/13] target/ppc: Split out gen_st_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 08/13] target/ppc: Split out gen_ld_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 10/13] target/ppc: Use MO_ALIGN for EXIWX and ECOWX, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 12/13] target/ppc: Implement the rest of gen_ld_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 04/13] target/ppc: Use atomic cmpxchg for STQCX, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 11/13] target/ppc: Use atomic min/max helpers, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 13/13] target/ppc: Implement the rest of gen_st_atomic,
Richard Henderson <=
- Re: [Qemu-ppc] [PATCH 00/13] target/ppc improve atomic operations, David Gibson, 2018/06/29