Re: [Qemu-ppc] [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

[Greg Kurz]

On Wed, 6 Jun 2018 10:53:17 +1000
David Gibson <address@hidden> wrote:

> On Tue, Jun 05, 2018 at 06:46:12PM +0200, Greg Kurz wrote:
> > On Mon, 4 Jun 2018 10:53:22 +1000
> > David Gibson <address@hidden> wrote:
> >   
> > > On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote:  
> > > > According to PowerISA, the PIR register should be readable in privileged
> > > > mode also, not only in hypervisor privileged mode.
> > > > 
> > > > PowerISA 3.0 - 4.3.3 Processor Identification Register
> > > > 
> > > > "Read access to the PIR is privileged; write access is not
> > > > provided."    
> > > 
> > > Yes... but a little further down it says "The PIR is a hypervisor
> > > resource".  Looking at the older 2.07 ISA, it says that
> > > guest-supervisor mode reads to the PIR should be redirected to the
> > > GPIR register, which this change won't accomplish.
> > >   
> > 
> > Hmmm, there are two definitions for the PIR, one in Book III-S (4.3.3)
> > and one in Book III-E (5.3.3). It looks like you're referring to the
> > latter...
> > 
> > [Category:Embedded.Hypervisor]
> > Read accesses to the PIR in guest supervisor state are
> > mapped to the GPIR.
> > 
> > The Book III-S definition doesn't mention the GPIR.  
> 
> Oops, sorry.  Yes the GPIR stuff is only for BookE.  The statement
> about the PIR being a hypervisor resource is definitely in the BookS
> section, however (both 2.07 and 3.0).
> 

Yes it is, but IIUC, this means that the guest cannot modify it, eg,
do mtspr. Section 4.4.4 in Book III-S has a list of SPRs that seem to
indicate that mfspr doesn't require hypervisor state with the PIR.

FWIW, this can be verified with xmon in a KVM guest:

0:mon> S
...
srr0   = c0000000000cd06c  srr1  = 8000000000001033 dsisr  = 00000000
dscr   = 0000000000000000  ppr   = 0010000000000000 pir    = 00000020
...
0:mon> Sr 3ff
SPR 0x3ff (1023) = 0x20

but with TCG xmon hits a program check:

0:mon> S
...
srr0   = c0000000000ef204  srr1  = 8000000000041033 dsisr  = 40000000
cpu 0x0: Vector: 700 (Program Check) at [c00000003ffdf510]
...
cpu 0x0: Exception 700 (Program Check) in xmon, returning to main loop
...
0:mon> Sr 3ff
SPR 0x3ff (1023) Faulted during read

This patch makes xmon happy under TCG.

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