Re: [Qemu-ppc] [Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

[David Gibson]

On Tue, Jun 05, 2018 at 06:46:12PM +0200, Greg Kurz wrote:
> On Mon, 4 Jun 2018 10:53:22 +1000
> David Gibson <address@hidden> wrote:
> 
> > On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote:
> > > According to PowerISA, the PIR register should be readable in privileged
> > > mode also, not only in hypervisor privileged mode.
> > > 
> > > PowerISA 3.0 - 4.3.3 Processor Identification Register
> > > 
> > > "Read access to the PIR is privileged; write access is not
> > > provided."  
> > 
> > Yes... but a little further down it says "The PIR is a hypervisor
> > resource".  Looking at the older 2.07 ISA, it says that
> > guest-supervisor mode reads to the PIR should be redirected to the
> > GPIR register, which this change won't accomplish.
> > 
> 
> Hmmm, there are two definitions for the PIR, one in Book III-S (4.3.3)
> and one in Book III-E (5.3.3). It looks like you're referring to the
> latter...
> 
> [Category:Embedded.Hypervisor]
> Read accesses to the PIR in guest supervisor state are
> mapped to the GPIR.
> 
> The Book III-S definition doesn't mention the GPIR.

Oops, sorry.  Yes the GPIR stuff is only for BookE.  The statement
about the PIR being a hypervisor resource is definitely in the BookS
section, however (both 2.07 and 3.0).

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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