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[Qemu-ppc] [PULL 07/17] spapr: Make a helper to set up cpu entry point s
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 07/17] spapr: Make a helper to set up cpu entry point state |
Date: |
Fri, 4 May 2018 15:59:20 +1000 |
Under PAPR, only the boot CPU is active when the system starts. Other cpus
must be explicitly activated using an RTAS call. The entry state for the
boot and secondary cpus isn't identical, but it has some things in common.
We're going to add a bit more common setup later, too, so to simplify
make a helper which sets up the common entry state for both boot and
secondary cpu threads.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
hw/ppc/spapr.c | 4 +---
hw/ppc/spapr_cpu_core.c | 9 +++++++++
hw/ppc/spapr_rtas.c | 6 ++----
include/hw/ppc/spapr_cpu_core.h | 3 +++
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index ed9b6a9535..535d8276df 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1668,10 +1668,8 @@ static void spapr_machine_reset(void)
g_free(fdt);
/* Set up the entry state */
- first_ppc_cpu->env.gpr[3] = fdt_addr;
+ spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
first_ppc_cpu->env.gpr[5] = 0;
- first_cpu->halted = 0;
- first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
spapr->cas_reboot = false;
}
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 01dbc69424..a98c7b04c6 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -52,6 +52,15 @@ static void spapr_cpu_reset(void *opaque)
}
+void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong
r3)
+{
+ CPUPPCState *env = &cpu->env;
+
+ env->nip = nip;
+ env->gpr[3] = r3;
+ CPU(cpu)->halted = 0;
+}
+
static void spapr_cpu_destroy(PowerPCCPU *cpu)
{
qemu_unregister_reset(spapr_cpu_reset, cpu);
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index df073447c5..840d198a8d 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -37,6 +37,7 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_vio.h"
#include "hw/ppc/spapr_rtas.h"
+#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/ppc.h"
#include "hw/boards.h"
@@ -173,10 +174,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu,
sPAPRMachineState *spapr,
*/
newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset;
- env->nip = start;
- env->gpr[3] = r3;
-
- CPU(newcpu)->halted = 0;
+ spapr_cpu_set_entry_state(newcpu, start, r3);
qemu_cpu_kick(CPU(newcpu));
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index 1129f344aa..47dcfda12b 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -12,6 +12,7 @@
#include "hw/qdev.h"
#include "hw/cpu/core.h"
#include "target/ppc/cpu-qom.h"
+#include "target/ppc/cpu.h"
#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
#define SPAPR_CPU_CORE(obj) \
@@ -38,4 +39,6 @@ typedef struct sPAPRCPUCoreClass {
} sPAPRCPUCoreClass;
const char *spapr_get_cpu_core_type(const char *cpu_type);
+void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong
r3);
+
#endif
--
2.17.0
- [Qemu-ppc] [PULL 00/17] ppc-for-2.13 queue 20180504, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 01/17] target/ppc: return a nil HPT base address on sPAPR machines, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 02/17] target/ppc: add basic support for PTCR on POWER9, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 03/17] spapr: Remove support for explicitly allocated RMAs, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 05/17] spapr: Clean up rtas_start_cpu() & rtas_stop_self(), David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 07/17] spapr: Make a helper to set up cpu entry point state,
David Gibson <=
- [Qemu-ppc] [PULL 11/17] spapr: Clean up handling of LPCR power-saving exit bits, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 15/17] target/ppc: always set PPC_MEM_TLBIE in pre 2.8 migration hack, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 16/17] spapr: don't migrate "spapr_option_vector_ov5_cas" to pre 2.8 machines, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 04/17] target/ppc: Add ppc_store_lpcr() helper, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 17/17] spapr: don't advertise radix GTSE if max-compat-cpu < power9, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 14/17] mac_newworld: move wiring of macio IRQs to macio_newworld_realize(), David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 10/17] spapr: Move PAPR mode cpu setup fully to spapr code, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 12/17] uninorth: create new uninorth device, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 09/17] target/ppc: Delay initialization of LPCR_UPRT for secondary cpus, David Gibson, 2018/05/04
- [Qemu-ppc] [PULL 06/17] spapr: Remove unhelpful helpers from rtas_start_cpu(), David Gibson, 2018/05/04