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[Qemu-ppc] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86 |
Date: |
Thu, 11 May 2017 14:14:09 +1000 |
From: Nikunj A Dadhania <address@hidden>
This enables the multi-threaded system emulation by default for PPC64
guests using the x86_64 TCG back-end.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
configure | 2 ++
target/ppc/cpu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configure b/configure
index 7c020c0..84c37d4 100755
--- a/configure
+++ b/configure
@@ -6110,12 +6110,14 @@ case "$target_name" in
ppc64)
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
+ mttcg=yes
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml
power-spe.xml power-vsx.xml"
;;
ppc64le)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
+ mttcg=yes
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml
power-spe.xml power-vsx.xml"
;;
ppc64abi32)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e0ff041..ece535d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -30,6 +30,8 @@
#define TARGET_LONG_BITS 64
#define TARGET_PAGE_BITS 12
+#define TCG_GUEST_DEFAULT_MO 0
+
/* Note that the official physical address space bits is 62-M where M
is implementation dependent. I've not looked up M for the set of
cpus we emulate at the system level. */
--
2.9.3
- [Qemu-ppc] [PULL 00/23] ppc-for-2.10 queue 20170511, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 04/23] target/ppc: Generate fence operations, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 03/23] cputlb: handle first atomic write to the page, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 19/23] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 05/23] cpus: Fix CPU unplug for MTTCG, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86,
David Gibson <=
- [Qemu-ppc] [PULL 10/23] Add QemuMacDrivers as submodule, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 21/23] target/ppc: Allow workarounds for POWER9 DD1, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 14/23] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 17/23] target/ppc: Implement ISA V3.00 radix page fault handler, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 16/23] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 20/23] spapr: Don't accidentally advertise HTM support on POWER9, David Gibson, 2017/05/11