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[Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data s
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv |
Date: |
Wed, 1 Mar 2017 17:54:35 +1100 |
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Balbir Singh <address@hidden>
---
V4 -> V5:
- Nothing
V3 -> V4:
- Use if instead of switch for mmu model
---
target/ppc/mmu-hash64.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 6261bac..0af59f1 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -606,7 +606,12 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState
*env,
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ } else {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@@ -624,7 +629,12 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState
*env, uint64_t dar,
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ if (env->mmu_model & POWERPC_MMU_V3) {
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ } else {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;
--
2.5.5
- [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 1/9] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 2/9] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 3/9] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv,
Suraj Jitindar Singh <=
- [Qemu-ppc] [PATCH V5 4/9] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 6/9] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 5/9] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 7/9] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 8/9] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V5 9/9] hw/ppc/spapr: Add POWER9 to pseries cpu models, Suraj Jitindar Singh, 2017/03/01
- Re: [Qemu-ppc] [PATCH V5 0/9] target/ppc: Implement POWER9 pseries TCG legacy support, David Gibson, 2017/03/01