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Re: [Qemu-ppc] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model a
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-ppc] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt |
Date: |
Fri, 14 Oct 2016 18:13:36 +1100 |
On Fri, 2016-10-14 at 17:32 +1100, David Gibson wrote:
> > static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
> > {
> > - /* We don't yet emulate the PSI bridge which provides the external
> > - * interrupt, so just drop interrupts on the floor
> > - */
> > + static uint32_t irqstate;
>
> Hmm.. static local with important state? That it's not clear whether
> it should be per-chip or not?
>
> I'm not averse to hacks for early bringup, but it should at least have
> a FIXME comment on it.
This emulates the external FPGA no ? There's only ever one ... well I
suppose one could make a machine with more but that hasn't been done
yet.
Ideally it could be a whole device by itself who feeds the ISA irqs and
outputs the final IRQ but that's overkill.
Cheers,
Ben.
[Qemu-ppc] [PATCH v4 18/20] ppc/pnv: Add OCC model stub with interrupt support, Cédric Le Goater, 2016/10/03
[Qemu-ppc] [PATCH v4 19/20] ppc/pnv: Add Naples chip support for LPC interrupts, Cédric Le Goater, 2016/10/03
[Qemu-ppc] [PATCH v4 20/20] ppc/pnv: add support for POWER9 LPC Controller, Cédric Le Goater, 2016/10/03