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[Qemu-ppc] [PULL 43/64] ppc: load/store multiple and string insns don't
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 43/64] ppc: load/store multiple and string insns don't do LE |
Date: |
Wed, 7 Sep 2016 20:29:22 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Just generate an alignment interrupt
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1315656..379d3d4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2889,6 +2889,11 @@ static void gen_lmw(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rD(ctx->opcode));
@@ -2903,6 +2908,11 @@ static void gen_stmw(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rS(ctx->opcode));
@@ -2929,6 +2939,10 @@ static void gen_lswi(DisasContext *ctx)
int ra = rA(ctx->opcode);
int nr;
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
if (nb == 0)
nb = 32;
nr = (nb + 3) / 4;
@@ -2952,6 +2966,11 @@ static void gen_lswx(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1, t2, t3;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -2971,6 +2990,11 @@ static void gen_stswi(DisasContext *ctx)
TCGv t0;
TCGv_i32 t1, t2;
int nb = NB(ctx->opcode);
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_register(ctx, t0);
@@ -2989,6 +3013,11 @@ static void gen_stswx(DisasContext *ctx)
{
TCGv t0;
TCGv_i32 t1, t2;
+
+ if (ctx->le_mode) {
+ gen_align_no_le(ctx);
+ return;
+ }
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
--
2.7.4
- [Qemu-ppc] [PULL 64/64] tests: Check serial output of firmware boot of some machines, (continued)
- [Qemu-ppc] [PULL 64/64] tests: Check serial output of firmware boot of some machines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 06/64] target-ppc: add cmprb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 56/64] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 42/64] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 51/64] target-ppc: add extswsli[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 43/64] ppc: load/store multiple and string insns don't do LE,
David Gibson <=
- [Qemu-ppc] [PULL 49/64] target-ppc: add vslv instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 24/64] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 59/64] ppc: Improve flags for helpers loading/writing the time facilities, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 22/64] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 63/64] tests: Resort check-qtest entries in Makefile.include, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 54/64] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/07