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[Qemu-ppc] [PULL 35/64] ppc: Don't update NIP if not taking alignment ex
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions |
Date: |
Wed, 7 Sep 2016 20:29:14 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Move the NIP update to after the conditional branch so that we
don't do it if we aren't going to take the alignment exception
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 93cd98c..6320ae5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2414,12 +2414,11 @@ static inline void gen_check_align(DisasContext *ctx,
TCGv EA, int mask)
TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv_i32 t1, t2;
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
tcg_gen_andi_tl(t0, EA, mask);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
t2 = tcg_const_i32(0);
+ gen_update_nip(ctx, ctx->nip - 4);
gen_helper_raise_exception_err(cpu_env, t1, t2);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
--
2.7.4
- [Qemu-ppc] [PULL 61/64] ppc: Improve a few more helper flags, (continued)
- [Qemu-ppc] [PULL 61/64] ppc: Improve a few more helper flags, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 29/64] ppc: Make tlb_fill() use new exception helper, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 46/64] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 57/64] ppc: Stop dumping state on all exceptions in linux-user, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 64/64] tests: Check serial output of firmware boot of some machines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 06/64] target-ppc: add cmprb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions,
David Gibson <=
- [Qemu-ppc] [PULL 56/64] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 42/64] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 51/64] target-ppc: add extswsli[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 43/64] ppc: load/store multiple and string insns don't do LE, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 49/64] target-ppc: add vslv instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 24/64] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 59/64] ppc: Improve flags for helpers loading/writing the time facilities, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 22/64] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 63/64] tests: Resort check-qtest entries in Makefile.include, David Gibson, 2016/09/07