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[Qemu-ppc] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invali
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() |
Date: |
Fri, 29 Jan 2016 16:07:07 +1100 |
Currently both the tlbiva instruction (used on 44x chips) and the tlbie
instruction (used on hash MMU chips) are both handled via
ppc_tlb_invalidate_one(). This is silly, because they're invoked from
different places, and do different things.
Clean this up by separating out the tlbiva instruction into its own
handling. In fact the implementation is only a stub anyway.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/mmu_helper.c | 14 ++++++++++----
target-ppc/translate.c | 2 +-
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 869be15..e5a8f7b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -544,6 +544,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl)
DEF_HELPER_2(74xx_tlbi, void, env, tl)
DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 82ebe5d..04b1fe1 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1971,10 +1971,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
ppc6xx_tlb_invalidate_virt(env, addr, 1);
}
break;
- case POWERPC_MMU_BOOKE:
- /* XXX: TODO */
- cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
- break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
/* tlbie invalidate TLBs for all segments */
@@ -2116,6 +2112,16 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
ppc_tlb_invalidate_one(env, addr);
}
+void helper_tlbiva(CPUPPCState *env, target_ulong addr)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ /* tlbiva instruction only exists on BookE */
+ assert(env->mmu_model == POWERPC_MMU_BOOKE);
+ /* XXX: TODO */
+ cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
+}
+
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4be7eaa..a05a169 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -5904,7 +5904,7 @@ static void gen_tlbiva(DisasContext *ctx)
}
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+ gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
tcg_temp_free(t0);
#endif
}
--
2.5.0
- [Qemu-ppc] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load, (continued)
- [Qemu-ppc] [PULL 02/39] target-ppc: use cpu_write_xer() helper in cpu_post_load, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 10/39] spapr: Don't create ibm, dynamic-reconfiguration-memory w/o DR LMBs, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 16/39] pseries: Clean up error handling in xics_system_init(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 17/39] pseries: Clean up error reporting in ppc_spapr_init(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 07/39] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 08/39] spapr: Remove rtas_st_buffer_direct(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 19/39] target-ppc: kvm: fix floating point registers sync on little-endian hosts, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 31/39] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(),
David Gibson <=
- [Qemu-ppc] [PULL 29/39] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 18/39] pseries: Clean up error reporting in htab migration functions, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 24/39] target-ppc: gdbstub: fix spe registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 06/39] cuda: add missing fields to VMStateDescription, David Gibson, 2016/01/29