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[Qemu-ppc] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & P
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG |
Date: |
Fri, 29 Jan 2016 16:07:10 +1100 |
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
---
target-ppc/mmu-hash64.h | 2 ++
target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 34cf975..ab0f86b 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -48,6 +48,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
#define SLB_VSID_4K 0x0000000000000000ULL
#define SLB_VSID_64K 0x0000000000000110ULL
+#define SLB_VSID_16M 0x0000000000000100ULL
+#define SLB_VSID_16G 0x0000000000000120ULL
/*
* Hash page table definitions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 156d156..d557043 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8104,6 +8104,36 @@ static Property powerpc_servercpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifdef CONFIG_SOFTMMU
+static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
+ .sps = {
+ {
+ .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 },
+ { .page_shift = 16, .pte_enc = 0x7 },
+ { .page_shift = 24, .pte_enc = 0x38 }, },
+ },
+ {
+ .page_shift = 16, /* 64K */
+ .slb_enc = SLB_VSID_64K,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 },
+ { .page_shift = 24, .pte_enc = 0x8 }, },
+ },
+ {
+ .page_shift = 24, /* 16M */
+ .slb_enc = SLB_VSID_16M,
+ .enc = { { .page_shift = 24, .pte_enc = 0 }, },
+ },
+ {
+ .page_shift = 34, /* 16G */
+ .slb_enc = SLB_VSID_16G,
+ .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
+ },
+ }
+};
+#endif /* CONFIG_SOFTMMU */
+
static void init_proc_POWER7 (CPUPPCState *env)
{
init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
@@ -8167,6 +8197,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8247,6 +8278,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->sps = &POWER7_POWER8_sps;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
--
2.5.0
- [Qemu-ppc] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init(), (continued)
- [Qemu-ppc] [PULL 12/39] pseries: Clean up error handling of spapr_cpu_init(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 07/39] spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 08/39] spapr: Remove rtas_st_buffer_direct(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 19/39] target-ppc: kvm: fix floating point registers sync on little-endian hosts, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 39/39] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 31/39] target-ppc: Rework ppc_store_slb, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 35/39] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 29/39] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 18/39] pseries: Clean up error reporting in htab migration functions, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 24/39] target-ppc: gdbstub: fix spe registers for little-endian guests, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 38/39] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG,
David Gibson <=
- [Qemu-ppc] [PULL 36/39] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 30/39] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 03/39] macio: use the existing IDEDMA aiocb to hold the active DMA aiocb, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 06/39] cuda: add missing fields to VMStateDescription, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 01/39] target-ppc: Use sensible POWER8/POWER8E versions, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 15/39] pseries: Clean up error handling in spapr_rtas_register(), David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 09/39] spapr: Remove abuse of rtas_ld() in h_client_architecture_support, David Gibson, 2016/01/29
- [Qemu-ppc] [PULL 11/39] ppc: Clean up error handling in ppc_set_compat(), David Gibson, 2016/01/29