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[Qemu-ppc] [PULL 46/52] target-ppc: Optimize rlwnm MB=0 ME=31
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 46/52] target-ppc: Optimize rlwnm MB=0 ME=31 |
Date: |
Thu, 4 Sep 2014 19:20:34 +0200 |
From: Tom Musta <address@hidden>
Optimize the special case of rlwnm where MB=0 and ME=31. This can
be implemented using a ROTL.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 56 ++++++++++++++++++++++++++++++--------------------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 889e37d..57cb381 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1721,37 +1721,49 @@ static void gen_rlwinm(DisasContext *ctx)
static void gen_rlwnm(DisasContext *ctx)
{
uint32_t mb, me;
- TCGv t0;
-#if defined(TARGET_PPC64)
- TCGv t1;
-#endif
-
mb = MB(ctx->opcode);
me = ME(ctx->opcode);
- t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
+
+ if (likely(mb == 0 && me == 31)) {
+ TCGv_i32 t0, t1;
+ t0 = tcg_temp_new_i32();
+ t1 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
+ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_andi_i32(t0, t0, 0x1f);
+ tcg_gen_rotl_i32(t1, t1, t0);
+ tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ } else {
+ TCGv t0;
#if defined(TARGET_PPC64)
- t1 = tcg_temp_new_i64();
- tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], 32, 32);
- tcg_gen_rotl_i64(t0, t1, t0);
- tcg_temp_free_i64(t1);
-#else
- tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
+ TCGv t1;
#endif
- if (unlikely(mb != 0 || me != 31)) {
+
+ t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
#if defined(TARGET_PPC64)
- mb += 32;
- me += 32;
+ t1 = tcg_temp_new_i64();
+ tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
+ cpu_gpr[rS(ctx->opcode)], 32, 32);
+ tcg_gen_rotl_i64(t0, t1, t0);
+ tcg_temp_free_i64(t1);
+#else
+ tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
#endif
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- } else {
+ if (unlikely(mb != 0 || me != 31)) {
#if defined(TARGET_PPC64)
- tcg_gen_andi_tl(t0, t0, MASK(32, 63));
+ mb += 32;
+ me += 32;
#endif
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
+ tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
+ } else {
+ tcg_gen_andi_tl(t0, t0, MASK(32, 63));
+ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
+ }
+ tcg_temp_free(t0);
}
- tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
--
1.8.1.4
- [Qemu-ppc] [PULL 44/52] target-ppc: Special Case of rlwimi Should Use Deposit, (continued)
- [Qemu-ppc] [PULL 44/52] target-ppc: Special Case of rlwimi Should Use Deposit, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 36/52] PPC: mac99: Fix core99 timer frequency, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 31/52] target-ppc: Bug Fix: mulldo OV Detection, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 34/52] KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 28/52] target-ppc: Bug Fix: rlwimi, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 32/52] target-ppc: Bug Fix: srawi, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 43/52] spapr-vlan: Don't touch last entry in buffer list, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 42/52] spapr_pci: Fix config space corruption, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 48/52] target-ppc: Clean up mullwo, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 39/52] PPC: mac_nvram: Split NVRAM into OF and OSX parts, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 46/52] target-ppc: Optimize rlwnm MB=0 ME=31,
Alexander Graf <=
- [Qemu-ppc] [PULL 49/52] target-ppc: Implement mulldo with TCG, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 52/52] hypervisor property clashes with hypervisor node, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 45/52] target-ppc: Optimize rlwinm MB=0 ME=31, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 38/52] PPC: mac_nvram: Allow 2 and 4 byte accesses, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 41/52] PPC: Cuda: Use cuda timer to expose tbfreq to guest, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 47/52] target-ppc: Clean Up mullw, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 50/52] spapr_pci: map the MSI window in each PHB, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 40/52] PPC: Mac: Move tbfreq into local variable, Alexander Graf, 2014/09/04
- [Qemu-ppc] [PULL 51/52] PPC: Fix default config ordering and add eTSEC for ppc64, Alexander Graf, 2014/09/04
- Re: [Qemu-ppc] [PULL 00/52] ppc patch queue 2014-09-04, Peter Maydell, 2014/09/04