Re: [Qemu-ppc] [Qemu-devel] [PATCH 6/8] target-ppc: Bug Fix: mulldo OV Detection

[Richard Henderson]

On 08/11/2014 09:23 AM, Tom Musta wrote:
> Fix the code to properly detect overflow; the 128 bit signed
> product must have all zeroes or all ones in the first 65 bits
> otherwise OV should be set.
> 
> Signed-off-by: Tom Musta <address@hidden>
> ---
>  target-ppc/int_helper.c |   14 ++++++++++++--
>  1 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index f6e8846..e83a25d 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -32,12 +32,22 @@ uint64_t helper_mulldo(CPUPPCState *env, uint64_t arg1, 
> uint64_t arg2)
>      uint64_t tl;
>  
>      muls64(&tl, (uint64_t *)&th, arg1, arg2);
> -    /* If th != 0 && th != -1, then we had an overflow */
> -    if (likely((uint64_t)(th + 1) <= 1)) {
> +
> +    /* th should either contain all 1 bits or all 0 bits and should
> +     * match the sign bit of tl; otherwise we have overflowed. */
> +
> +    if ((int64_t)tl < 0) {
> +        if (likely(th == -1LL)) {
> +            env->ov = 0;
> +        } else {
> +            env->so = env->ov = 1;
> +        }
> +    } else if (likely(th == 0LL)) {
>          env->ov = 0;
>      } else {
>          env->so = env->ov = 1;
>      }
> +

As far as it goes,
Reviewed-by: Richard Henderson <address@hidden>

But we can just as easily implement this inline, as we do for mullwo.  We've
added a tcg_gen_muls2_i64 since this code was written.


r~