Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/8] target-ppc: Bug Fix: rlwinm

[Richard Henderson]

On 08/15/2014 08:34 AM, Richard Henderson wrote:
> On 08/11/2014 09:23 AM, Tom Musta wrote:
>> The rlwinm specification includes the ROTL32 operation, which is defined
>> to be a left rotation of two copies of the least significant 32 bits of
>> the source GPR.
>>
>> The current implementation is incorrect on 64-bit implementations in that
>> it rotates a single copy of the least significant 32 bits, padding with
>> zeroes in the most significant bits.
> 
> Yes, it does describe rotate_32 as a double-copy of the low 32 bits.  But it
> also describes the mask as having "0 bits elsewhere".  Thus, post mask, I 
> don't
> see how you could distinguish the implementations.
> 
> Have you an example that doesn't work with the current code?

Let me guess the answer myself -- it's MB > ME, and wraparound of the mask.

I think I was distracted by the text "For all the uses given above, the
high-order 32 bits of register RA are cleared." without clearly reading the
examples.


r~