[Qemu-ppc] [PATCH 5/7] Add lxvd2x

[Tom Musta]

This patch adds the lxvd2x instruction.

Signed-off-by: Tom Musta <address@hidden>

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index be3edc2..11e31c6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7007,6 +7007,22 @@ static inline TCGv_i64 cpu_vsrl(int n)
     }
 }

+static void gen_lxvd2x(DisasContext *ctx)
+{
+    TCGv EA;
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
+    tcg_gen_addi_tl(EA, EA, 8);
+    gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
+    tcg_temp_free(EA);
+}
+
 /***                           SPE 
extension                               ***/
 /* Register moves */

@@ -9456,6 +9472,11 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
 GEN_VAFORM_PAIRED(vsel, vperm, 21),
 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),

+#undef  GEN_VSX_LXVNX
+#define GEN_VSX_LXVNX(name, opc2, 
opc3)                                        \
+  GEN_HANDLER_E(lxv##name, 0x1F, opc2, opc3, 0x00000000, PPC_NONE, 
PPC2_VSX)
+
+GEN_VSX_LXVNX(d2x, 0x0C, 0x1A),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, 
type, PPC_NONE)
--
1.7.1