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[Qemu-ppc] [PATCH 4/7] Add VSR to Global Registers
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 4/7] Add VSR to Global Registers |
Date: |
Tue, 24 Sep 2013 10:03:56 -0500 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:17.0) Gecko/20130801 Thunderbird/17.0.8 |
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.
Signed-off-by: Tom Musta <address@hidden>
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d80ed8a..be3edc2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -51,6 +51,7 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */
#endif
+ 10*4 + 22*5 /* FPR */
+ 2*(10*6 + 22*7) /* AVRh, AVRl */
+ + 10*5 + 22*6 /* VSR */
+ 8*5 /* CRF */];
static TCGv cpu_gpr[32];
#if !defined(TARGET_PPC64)
@@ -58,6 +59,7 @@ static TCGv cpu_gprh[32];
#endif
static TCGv_i64 cpu_fpr[32];
static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
+static TCGv_i64 cpu_vsr[32];
static TCGv_i32 cpu_crf[8];
static TCGv cpu_nip;
static TCGv cpu_msr;
@@ -137,6 +139,11 @@ void ppc_translate_init(void)
#endif
p += (i < 10) ? 6 : 7;
cpu_reg_names_size -= (i < 10) ? 6 : 7;
+ snprintf(p, cpu_reg_names_size, "vsr%d", i);
+ cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUPPCState,
vsr[i]), p);
+ p += (i < 10) ? 5 : 6;
+ cpu_reg_names_size -= (i < 10) ? 5 : 6;
}
cpu_nip = tcg_global_mem_new(TCG_AREG0,
@@ -6980,6 +6987,26 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
+/*** VSX
extension ***/
+
+static inline TCGv_i64 cpu_vsrh(int n)
+{
+ if (n < 32) {
+ return cpu_fpr[n];
+ } else {
+ return cpu_avrh[n-32];
+ }
+}
+
+static inline TCGv_i64 cpu_vsrl(int n)
+{
+ if (n < 32) {
+ return cpu_vsr[n];
+ } else {
+ return cpu_avrl[n-32];
+ }
+}
+
/*** SPE
extension ***/
/* Register moves */
--
1.7.1
- [Qemu-ppc] [PATCH 0/7] Stage 1 VSX Support, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 1/7] Declare and Enable VSX, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 2/7] Add MSR VSX and Associated Exception, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 3/7] Add VSX Instruction Decoders, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 4/7] Add VSR to Global Registers,
Tom Musta <=
- [Qemu-ppc] [PATCH 5/7] Add lxvd2x, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 6/7] Add stxvd2x, Tom Musta, 2013/09/24
- [Qemu-ppc] [PATCH 7/7] Add xxpermdi, Tom Musta, 2013/09/24
- Re: [Qemu-ppc] [PATCH 0/7] Stage 1 VSX Support, Alexander Graf, 2013/09/25