Re: [Qemu-ppc] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.

[Scott Wood]

On 03/23/2012 08:29 AM, Mark Cave-Ayland wrote:
> On 22/03/12 20:32, Scott Wood wrote:
> 
> Hi Scott,
> 
>> As I think Alex commented recently, we really should be picking the bits
>> we want to keep rather than the ones we want to exclude.  Please keep in
>> mind that this code is used by booke as well.  E.g. on booke exceptions
>> don't normally clear MSR[DE], but it's in your mask of bits to clear.
>> The mask should depend on both the exception model and the specific
>> exception type.
> 
> Well this is the part that is currently confusing me; I know Alex
> mentioned about picking the bits to keep, however that appears to
> contradict the reference specification link he pointed me towards at
> https://www.power.org/resources/downloads/PowerISA_V2.06B_V2_PUBLIC.pdf,
> page 811. This states "The MSR is set as shown" referencing the table on
> page 814 showing the status of only 8 of the MSR bits. Therefore from
> this I would naturally conclude that the value of any other MSR bits
> should be preserved, not zeroed, as per Alex's comment and the existing
> implementation.

OK, this looks like a difference between book3s and book3e.

-Scott