Re: [Qemu-ppc] Regression in ppc-softmmu when running HelenOS

[Alexander Graf]

On 13.03.2012, at 12:54, Mark Cave-Ayland wrote:

> On 12/03/12 19:33, Alexander Graf wrote:
> 
>>> (Cc: to helenos-devel@)
>>> 
>>> I tried your patch with the latest HelenOS mainline. The user experience
>>> seems the same compared to what you get with Qemu 0.11.1, meaning that
>>> in both cases the clock seems to go too fast (could be a HelenOS bug),
>>> but otherwise the system boots and runs fine.
>> 
>> So we are losing an MSR bit. Please try to find out which one it is.
> 
> Hi Alex,
> 
> I can have a look at this and see if I can come up with something better. 
> However I am a little confused by your original patch which looks something 
> like this:
> 
> 
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
> 
> /* new interrupt handler msr */
> new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> ...
> ...
> /* Save MSR */
> env->spr[srr1] = msr;
> ...
> env->msr = new_msr & env->msr_mask;
> 
> 
> Based upon the logic at http://www.systemcomputing.org/ppc/ppc4.htm then it 
> would imply that env->msr should be placed unaltered into srr1 and then the 
> must-be-zero bits just masked out on new_msr? Or am I missing something here?

msr becomes srr1 (and masks the not-to-be-set bits out)
new_msr becomes the new MSR and only carries over MSR_ME from the current MSR

This looks correct to me. For reference, please check up page 811 on the 
PowerISA 2.06B:

  https://www.power.org/resources/downloads/PowerISA_V2.06B_V2_PUBLIC.pdf


Alex