[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 01/22] target/arm: Rename FPST_FPCR_A32 to FPST_A32
From: |
Richard Henderson |
Subject: |
[PATCH 01/22] target/arm: Rename FPST_FPCR_A32 to FPST_A32 |
Date: |
Mon, 27 Jan 2025 15:25:43 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.h | 6 ++--
target/arm/tcg/translate-vfp.c | 54 +++++++++++++++++-----------------
2 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 59e780df2e..6ce2471aa6 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -674,7 +674,7 @@ static inline CPUARMTBFlags arm_tbflags_from_tb(const
TranslationBlock *tb)
* Enum for argument to fpstatus_ptr().
*/
typedef enum ARMFPStatusFlavour {
- FPST_FPCR_A32,
+ FPST_A32,
FPST_FPCR_A64,
FPST_FPCR_F16_A32,
FPST_FPCR_F16_A64,
@@ -692,7 +692,7 @@ typedef enum ARMFPStatusFlavour {
* been set up to point to the requested field in the CPU state struct.
* The options are:
*
- * FPST_FPCR_A32
+ * FPST_A32
* for AArch32 non-FP16 operations controlled by the FPCR
* FPST_FPCR_A64
* for AArch64 non-FP16 operations controlled by the FPCR
@@ -717,7 +717,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
int offset;
switch (flavour) {
- case FPST_FPCR_A32:
+ case FPST_A32:
offset = offsetof(CPUARMState, vfp.fp_status_a32);
break;
case FPST_FPCR_A64:
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index 8eebba0f27..4cc12a407b 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -462,7 +462,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
if (sz == 1) {
fpst = fpstatus_ptr(FPST_FPCR_F16_A32);
} else {
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
}
tcg_rmode = gen_set_rmode(rounding, fpst);
@@ -529,7 +529,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
if (sz == 1) {
fpst = fpstatus_ptr(FPST_FPCR_F16_A32);
} else {
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
}
tcg_shift = tcg_constant_i32(0);
@@ -1398,7 +1398,7 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn
*fn,
f0 = tcg_temp_new_i32();
f1 = tcg_temp_new_i32();
fd = tcg_temp_new_i32();
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
vfp_load_reg32(f0, vn);
vfp_load_reg32(f1, vm);
@@ -1517,7 +1517,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn
*fn,
f0 = tcg_temp_new_i64();
f1 = tcg_temp_new_i64();
fd = tcg_temp_new_i64();
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
vfp_load_reg64(f0, vn);
vfp_load_reg64(f1, vm);
@@ -2181,7 +2181,7 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a,
bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negs(vd, vd);
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
vfp_store_reg32(vd, a->vd);
return true;
@@ -2246,7 +2246,7 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a,
bool neg_n, bool neg_d)
/* VFNMA, VFNMS */
gen_vfp_negd(vd, vd);
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
vfp_store_reg64(vd, a->vd);
return true;
@@ -2429,12 +2429,12 @@ static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR_A32));
+ gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_A32));
}
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{
- gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR_A32));
+ gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_A32));
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
@@ -2565,7 +2565,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s,
arg_VCVT_f32_f16 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
@@ -2599,7 +2599,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s,
arg_VCVT_f64_f16 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
/* The T bit tells us if we want the low or high 16 bits of Vm */
@@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s,
arg_VCVT_b16_f32 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
@@ -2646,7 +2646,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s,
arg_VCVT_f16_f32 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
@@ -2680,7 +2680,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s,
arg_VCVT_f16_f64 *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
ahp_mode = get_ahp_flag();
tmp = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
@@ -2727,7 +2727,7 @@ static bool trans_VRINTR_sp(DisasContext *s,
arg_VRINTR_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rints(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2757,7 +2757,7 @@ static bool trans_VRINTR_dp(DisasContext *s,
arg_VRINTR_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rintd(tmp, tmp, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
@@ -2803,7 +2803,7 @@ static bool trans_VRINTZ_sp(DisasContext *s,
arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2836,7 +2836,7 @@ static bool trans_VRINTZ_dp(DisasContext *s,
arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_restore_rmode(tcg_rmode, fpst);
@@ -2880,7 +2880,7 @@ static bool trans_VRINTX_sp(DisasContext *s,
arg_VRINTX_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rints_exact(tmp, tmp, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
@@ -2910,7 +2910,7 @@ static bool trans_VRINTX_dp(DisasContext *s,
arg_VRINTX_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
gen_helper_rintd_exact(tmp, tmp, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
@@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR_A32));
+ gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_A32));
vfp_store_reg64(vd, a->vd);
return true;
}
@@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm);
- gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR_A32));
+ gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_A32));
vfp_store_reg32(vd, a->vd);
return true;
}
@@ -3010,7 +3010,7 @@ static bool trans_VCVT_int_sp(DisasContext *s,
arg_VCVT_int_sp *a)
vm = tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
if (a->s) {
/* i32 -> f32 */
gen_helper_vfp_sitos(vm, vm, fpst);
@@ -3044,7 +3044,7 @@ static bool trans_VCVT_int_dp(DisasContext *s,
arg_VCVT_int_dp *a)
vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
if (a->s) {
/* i32 -> f64 */
gen_helper_vfp_sitod(vd, vm, fpst);
@@ -3161,7 +3161,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s,
arg_VCVT_fix_sp *a)
vd = tcg_temp_new_i32();
vfp_load_reg32(vd, a->vd);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
shift = tcg_constant_i32(frac_bits);
/* Switch on op:U:sx bits */
@@ -3223,7 +3223,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s,
arg_VCVT_fix_dp *a)
vd = tcg_temp_new_i64();
vfp_load_reg64(vd, a->vd);
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
shift = tcg_constant_i32(frac_bits);
/* Switch on op:U:sx bits */
@@ -3307,7 +3307,7 @@ static bool trans_VCVT_sp_int(DisasContext *s,
arg_VCVT_sp_int *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
vm = tcg_temp_new_i32();
vfp_load_reg32(vm, a->vm);
@@ -3347,7 +3347,7 @@ static bool trans_VCVT_dp_int(DisasContext *s,
arg_VCVT_dp_int *a)
return true;
}
- fpst = fpstatus_ptr(FPST_FPCR_A32);
+ fpst = fpstatus_ptr(FPST_A32);
vm = tcg_temp_new_i64();
vd = tcg_temp_new_i32();
vfp_load_reg64(vm, a->vm);
--
2.43.0
- [PATCH 00/22] target/arm: FEAT_AFP followups for FEAT_SME2, Richard Henderson, 2025/01/27
- [PATCH 01/22] target/arm: Rename FPST_FPCR_A32 to FPST_A32,
Richard Henderson <=
- [PATCH 03/22] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16, Richard Henderson, 2025/01/27
- [PATCH 05/22] target/arm: Rename FPST_FPCR_AH* to FPST_AH*, Richard Henderson, 2025/01/27
- [PATCH 02/22] target/arm: Rename FPST_FPCR_A64 to FPST_A64, Richard Henderson, 2025/01/27
- [PATCH 07/22] target/arm: Remove standard_fp_status_f16, Richard Henderson, 2025/01/27
- [PATCH 16/22] target/arm: Simplify DO_VFP_cmp in vfp_helper.c, Richard Henderson, 2025/01/27
- [PATCH 18/22] target/arm: Introduce float*_maybe_ah_chs, Richard Henderson, 2025/01/27
- [PATCH 06/22] target/arm: Introduce CPUARMState.vfp.fp_status[], Richard Henderson, 2025/01/27
- [PATCH 04/22] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16, Richard Henderson, 2025/01/27
- [PATCH 08/22] target/arm: Remove standard_fp_status, Richard Henderson, 2025/01/27