Re: [PATCH 65/76] target/arm: Handle FPCR.AH in negation step in SVE FMLS (vector)

[Richard Henderson]

On 1/24/25 08:28, Peter Maydell wrote:
> @@ -4910,9 +4958,15 @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void 
> *vm, void *va, void *vg,
>               if (likely((pg >> (i & 63)) & 1)) {
>                   float64 e1, e2, e3, r;
>   
> -                e1 = *(uint64_t *)(vn + i) ^ neg1;
> +                e1 = *(uint64_t *)(vn + i);
>                   e2 = *(uint64_t *)(vm + i);
> -                e3 = *(uint64_t *)(va + i) ^ neg3;
> +                e3 = *(uint64_t *)(va + i);
> +                if (neg1 && !(fpcr_ah && float64_is_any_nan(e1))) {
> +                    e1 ^= neg1;
> +                }
> +                if (neg3 && !(fpcr_ah && float64_is_any_nan(e3))) {
> +                    e3 ^= neg3;
> +                }
>                   r = float64_muladd(e1, e2, e3, 0, status);

It occurs to me that with AH=1, we can use the float_muladd_* flags.
We couldn't use those for AH=0, because there we *need* to negate NaNs.


r~