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[PATCH v7 45/52] i386/tdx: Mask off CPUID bits by unsupported XFAM
From: |
Xiaoyao Li |
Subject: |
[PATCH v7 45/52] i386/tdx: Mask off CPUID bits by unsupported XFAM |
Date: |
Fri, 24 Jan 2025 08:20:41 -0500 |
Mask off the CPUID bits as unsupported if its matched XFAM bit is
not supported. Otherwise, it might fail the check in setup_td_xfam() as
unsupported XFAM being requested.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/kvm/tdx.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 3997a439f054..b46e581bb40e 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -22,6 +22,8 @@
#include <linux/kvm_para.h>
+#include "cpu.h"
+#include "cpu-internal.h"
#include "hw/i386/e820_memory_layout.h"
#include "hw/i386/x86.h"
#include "hw/i386/tdvf.h"
@@ -579,6 +581,42 @@ static void tdx_mask_cpuid_by_attrs(uint32_t feature,
uint32_t index,
}
}
+static void tdx_mask_cpuid_by_xfam(uint32_t feature, uint32_t index,
+ int reg, uint32_t *value)
+{
+ const FeatureWordInfo *f;
+ const ExtSaveArea *esa;
+ uint64_t unavail = 0;
+ int i;
+
+ assert(tdx_caps);
+
+ for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
+ if ((1ULL << i) & tdx_caps->supported_xfam) {
+ continue;
+ }
+
+ if (!((1ULL << i) & CPUID_XSTATE_MASK)) {
+ continue;
+ }
+
+ esa = &x86_ext_save_areas[i];
+ f = &feature_word_info[esa->feature];
+ assert(f->type == CPUID_FEATURE_WORD);
+ if (f->cpuid.eax != feature ||
+ (f->cpuid.needs_ecx && f->cpuid.ecx != index) ||
+ f->cpuid.reg != reg) {
+ continue;
+ }
+
+ unavail |= esa->bits;
+ }
+
+ if (unavail) {
+ *value &= ~unavail;
+ }
+}
+
static uint32_t tdx_adjust_cpuid_features(X86ConfidentialGuest *cg,
uint32_t feature, uint32_t index,
int reg, uint32_t value)
@@ -613,6 +651,7 @@ static uint32_t
tdx_adjust_cpuid_features(X86ConfidentialGuest *cg,
}
tdx_mask_cpuid_by_attrs(feature, index, reg, &value);
+ tdx_mask_cpuid_by_xfam(feature, index, reg, &value);
e = cpuid_find_entry(&tdx_fixed0_bits.cpuid, feature, index);
if (e) {
--
2.34.1
- [PATCH v7 32/52] i386/tdx: Force exposing CPUID 0x1f, (continued)
- [PATCH v7 32/52] i386/tdx: Force exposing CPUID 0x1f, Xiaoyao Li, 2025/01/24
- [PATCH v7 34/52] i386/tdx: Disable SMM for TDX VMs, Xiaoyao Li, 2025/01/24
- [PATCH v7 39/52] cpu: Don't set vcpu_dirty when guest_state_protected, Xiaoyao Li, 2025/01/24
- [PATCH v7 42/52] i386/tdx: Apply TDX fixed0 and fixed1 information to supported CPUIDs, Xiaoyao Li, 2025/01/24
- [PATCH v7 41/52] i386/tdx: Implement adjust_cpuid_features() for TDX, Xiaoyao Li, 2025/01/24
- [PATCH v7 49/52] i386/tdx: Don't treat SYSCALL as unavailable, Xiaoyao Li, 2025/01/24
- [PATCH v7 43/52] i386/tdx: Mask off CPUID bits by unsupported TD Attributes, Xiaoyao Li, 2025/01/24
- [PATCH v7 44/52] i386/cpu: Move CPUID_XSTATE_XSS_MASK to header file and introduce CPUID_XSTATE_MASK, Xiaoyao Li, 2025/01/24
- [PATCH v7 46/52] i386/tdx: Mark the configurable bit not reported by KVM as unsupported, Xiaoyao Li, 2025/01/24
- [PATCH v7 40/52] i386/cgs: Rename *mask_cpuid_features() to *adjust_cpuid_features(), Xiaoyao Li, 2025/01/24
- [PATCH v7 45/52] i386/tdx: Mask off CPUID bits by unsupported XFAM,
Xiaoyao Li <=
- [PATCH v7 47/52] i386/cgs: Introduce x86_confidential_guest_check_features(), Xiaoyao Li, 2025/01/24
- [PATCH v7 50/52] i386/tdx: Make invtsc default on, Xiaoyao Li, 2025/01/24
- [PATCH v7 51/52] i386/tdx: Validate phys_bits against host value, Xiaoyao Li, 2025/01/24
- [PATCH v7 48/52] i386/tdx: Fetch and validate CPUID of TD guest, Xiaoyao Li, 2025/01/24
- [PATCH v7 52/52] docs: Add TDX documentation, Xiaoyao Li, 2025/01/24