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[PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style
From: |
Jamin Lin |
Subject: |
[PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style |
Date: |
Tue, 21 Jan 2025 15:04:21 +0800 |
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_hace.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -75,9 +75,12 @@ static const struct {
{ HASH_ALGO_SHA1, QCRYPTO_HASH_ALGO_SHA1 },
{ HASH_ALGO_SHA224, QCRYPTO_HASH_ALGO_SHA224 },
{ HASH_ALGO_SHA256, QCRYPTO_HASH_ALGO_SHA256 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,
QCRYPTO_HASH_ALGO_SHA512 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,
QCRYPTO_HASH_ALGO_SHA384 },
- { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,
QCRYPTO_HASH_ALGO_SHA256 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512,
+ QCRYPTO_HASH_ALGO_SHA512 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384,
+ QCRYPTO_HASH_ALGO_SHA384 },
+ { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256,
+ QCRYPTO_HASH_ALGO_SHA256 },
};
static int hash_algo_lookup(uint32_t reg)
@@ -201,7 +204,8 @@ static void do_hash_operation(AspeedHACEState *s, int algo,
bool sg_mode,
haddr = address_space_map(&s->dram_as, addr, &plen, false,
MEMTXATTRS_UNSPECIFIED);
if (haddr == NULL) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n",
__func__);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: qcrypto failed\n", __func__);
return;
}
iov[i].iov_base = haddr;
--
2.34.1
- [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling, (continued)
- [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling, Jamin Lin, 2025/01/21
- [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging, Jamin Lin, 2025/01/21
- [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller, Jamin Lin, 2025/01/21
- [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions, Jamin Lin, 2025/01/21
- [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1, Jamin Lin, 2025/01/21
- [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0, Jamin Lin, 2025/01/21
- [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1, Jamin Lin, 2025/01/21
- [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style,
Jamin Lin <=
- [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support, Jamin Lin, 2025/01/21
- [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700, Jamin Lin, 2025/01/21
- [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND), Jamin Lin, 2025/01/21
- Re: [PATCH v1 00/18] Support AST2700 A1, Cédric Le Goater, 2025/01/31