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[PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduc
From: |
Jamin Lin |
Subject: |
[PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication |
Date: |
Tue, 21 Jan 2025 15:04:13 +0800 |
The behavior of the INTC set IRQ is almost identical between INTC0 and INTC1.
To reduce duplicated code, introduce the `aspeed_intc_set_irq_handler` function
to handle both INTC0 and INTC1 IRQ behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 56 +++++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 45f1c59a4b..8684d41ef6 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -91,11 +91,36 @@ static void aspeed_intc_update(AspeedINTCState *s, int
inpin_idx,
qemu_set_irq(s->output_pins[outpin_idx], level);
}
+static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
+ const AspeedINTCIRQ *irq, uint32_t select)
+{
+ if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
+ /*
+ * a. mask is not 0 means in ISR mode
+ * sources interrupt routine are executing.
+ * b. status register value is not 0 means previous
+ * source interrupt does not be executed, yet.
+ *
+ * save source interrupt to pending variable.
+ */
+ s->pending[irq->inpin_idx] |= select;
+ trace_aspeed_intc_pending_irq(irq->inpin_idx,
+ s->pending[irq->inpin_idx]);
+ } else {
+ /*
+ * notify firmware which source interrupt are coming
+ * by setting status register
+ */
+ s->regs[irq->status_addr] = select;
+ trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
+ s->regs[irq->status_addr]);
+ aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
+ }
+}
+
/*
- * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
- * Utilize "address & 0x0f00" to get the irq and irq output pin index
- * The value of irq should be 0 to num_ints.
- * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
+ * GICINT128 to GICINT136 map 1:1 to input and output IRQs 0 to 8.
+ * The value of input IRQ should be between 0 and the number of inputs.
*/
static void aspeed_intc_set_irq(void *opaque, int irq_idx, int level)
{
@@ -136,28 +161,7 @@ static void aspeed_intc_set_irq(void *opaque, int irq_idx,
int level)
trace_aspeed_intc_select(select);
- if (s->mask[irq->inpin_idx] || s->regs[irq->status_addr]) {
- /*
- * a. mask is not 0 means in ISR mode
- * sources interrupt routine are executing.
- * b. status register value is not 0 means previous
- * source interrupt does not be executed, yet.
- *
- * save source interrupt to pending variable.
- */
- s->pending[irq->inpin_idx] |= select;
- trace_aspeed_intc_pending_irq(irq->inpin_idx,
- s->pending[irq->inpin_idx]);
- } else {
- /*
- * notify firmware which source interrupt are coming
- * by setting status register
- */
- s->regs[irq->status_addr] = select;
- trace_aspeed_intc_trigger_irq(irq->inpin_idx, irq->outpin_idx,
- s->regs[irq->status_addr]);
- aspeed_intc_update(s, irq->inpin_idx, irq->outpin_idx, 1);
- }
+ aspeed_intc_set_irq_handler(s, irq, select);
}
static void aspeed_2700_intc_enable_handler(AspeedINTCState *s, uint32_t addr,
--
2.34.1
- Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0, (continued)
- [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops, Jamin Lin, 2025/01/21
- [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0, Jamin Lin, 2025/01/21
- [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers, Jamin Lin, 2025/01/21
- [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size, Jamin Lin, 2025/01/21
- [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address, Jamin Lin, 2025/01/21
- [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication,
Jamin Lin <=
- [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling, Jamin Lin, 2025/01/21
- [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging, Jamin Lin, 2025/01/21
- [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller, Jamin Lin, 2025/01/21
- [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions, Jamin Lin, 2025/01/21
- [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1, Jamin Lin, 2025/01/21
- [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0, Jamin Lin, 2025/01/21
- [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1, Jamin Lin, 2025/01/21