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[PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops f
From: |
Jamin Lin |
Subject: |
[PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 |
Date: |
Tue, 21 Jan 2025 15:04:09 +0800 |
Rename "aspeed_intc_read" to "aspeed_2700_intc0_read" and "aspeed_intc_write" to
"aspeed_2700_intc0_write".
Introduce a new memory region operation, "aspeed_2700_intc0_ops", for the
AST2700 INTC0 model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 628f69ea88..219ca02940 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -114,7 +114,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int
level)
}
}
-static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int
size)
+static uint64_t aspeed_2700_intc0_read(void *opaque, hwaddr offset,
+ unsigned int size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
uint32_t addr = offset >> 2;
@@ -133,8 +134,8 @@ static uint64_t aspeed_intc_read(void *opaque, hwaddr
offset, unsigned int size)
return value;
}
-static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
- unsigned size)
+static void aspeed_2700_intc0_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
{
AspeedINTCState *s = ASPEED_INTC(opaque);
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
@@ -261,8 +262,6 @@ static void aspeed_intc_write(void *opaque, hwaddr offset,
uint64_t data,
}
static const MemoryRegionOps aspeed_intc_ops = {
- .read = aspeed_intc_read,
- .write = aspeed_intc_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -339,6 +338,16 @@ static const TypeInfo aspeed_intc_info = {
.abstract = true,
};
+static const MemoryRegionOps aspeed_2700_intc0_ops = {
+ .read = aspeed_2700_intc0_read,
+ .write = aspeed_2700_intc0_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
static void aspeed_2700_intc0_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -347,6 +356,7 @@ static void aspeed_2700_intc0_class_init(ObjectClass
*klass, void *data)
dc->desc = "ASPEED 2700 INTC 0 Controller";
aic->num_lines = 32;
aic->num_ints = 9;
+ aic->reg_ops = &aspeed_2700_intc0_ops;
}
static const TypeInfo aspeed_2700_intc0_info = {
--
2.34.1
- [PATCH v1 00/18] Support AST2700 A1, Jamin Lin, 2025/01/21
- [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0, Jamin Lin, 2025/01/21
- [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops, Jamin Lin, 2025/01/21
- [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0,
Jamin Lin <=
- [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers, Jamin Lin, 2025/01/21
- [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size, Jamin Lin, 2025/01/21
- [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address, Jamin Lin, 2025/01/21
- [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication, Jamin Lin, 2025/01/21
- [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling, Jamin Lin, 2025/01/21
- [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging, Jamin Lin, 2025/01/21
- [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller, Jamin Lin, 2025/01/21
- [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions, Jamin Lin, 2025/01/21