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[PULL 06/50] target/riscv: add shtvala
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From: |
Alistair Francis |
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Subject: |
[PULL 06/50] target/riscv: add shtvala |
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Date: |
Fri, 17 Jan 2025 15:55:08 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
shtvala is described in RVA22 as:
"htval must be written with the faulting guest physical address
in all circumstances permitted by the ISA."
This is the case since commit 3067553993, so claim support for shtvala.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 356 -> 364 bytes
2 files changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4f76efc298..fe5f7b572f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
diff --git a/tests/data/acpi/riscv64/virt/RHCT
b/tests/data/acpi/riscv64/virt/RHCT
index 15b82b5bb1..065f894010 100644
Binary files a/tests/data/acpi/riscv64/virt/RHCT and
b/tests/data/acpi/riscv64/virt/RHCT differ
--
2.47.1
- [PULL 00/50] riscv-to-apply queue, Alistair Francis, 2025/01/17
- [PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names, Alistair Francis, 2025/01/17
- [PULL 02/50] target/riscv: rvv: speed up small unit-stride loads and stores, Alistair Francis, 2025/01/17
- [PULL 03/50] riscv/gdbstub: add V bit to priv reg, Alistair Francis, 2025/01/17
- [PULL 04/50] target/riscv: add shcounterenw, Alistair Francis, 2025/01/17
- [PULL 05/50] target/riscv: add shvstvala, Alistair Francis, 2025/01/17
- [PULL 06/50] target/riscv: add shtvala,
Alistair Francis <=
- [PULL 07/50] target/riscv: add shvstvecd, Alistair Francis, 2025/01/17
- [PULL 08/50] target/riscv: add shvsatpa, Alistair Francis, 2025/01/17
- [PULL 09/50] target/riscv: add shgatpa, Alistair Francis, 2025/01/17
- [PULL 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/17
- [PULL 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/17
- [PULL 12/50] target/riscv: add trace in riscv_raise_exception(), Alistair Francis, 2025/01/17
- [PULL 13/50] target/riscv: Remove obsolete pointer masking extension code., Alistair Francis, 2025/01/17
- [PULL 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/17
- [PULL 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/17
- [PULL 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/17