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[PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst functio
From: |
Alistair Francis |
Subject: |
[PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names |
Date: |
Fri, 17 Jan 2025 15:55:03 +1000 |
From: Craig Blackmore <craig.blackmore@embecosm.com>
Replace `continus` with `continuous`.
Signed-off-by: Craig Blackmore <craig.blackmore@embecosm.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241218142353.1027938-2-craig.blackmore@embecosm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a85dd1d200..0f57e48cc5 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -195,7 +195,7 @@ GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl)
GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq)
static inline QEMU_ALWAYS_INLINE void
-vext_continus_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,
+vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,
void *vd, uint32_t evl, target_ulong addr,
uint32_t reg_start, uintptr_t ra, uint32_t esz,
bool is_load)
@@ -207,7 +207,7 @@ vext_continus_ldst_tlb(CPURISCVState *env,
vext_ldst_elem_fn_tlb *ldst_tlb,
}
static inline QEMU_ALWAYS_INLINE void
-vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
+vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host
*ldst_host,
void *vd, uint32_t evl, uint32_t reg_start, void *host,
uint32_t esz, bool is_load)
{
@@ -342,8 +342,8 @@ vext_page_ldst_us(CPURISCVState *env, void *vd,
target_ulong addr,
if (flags == 0) {
if (nf == 1) {
- vext_continus_ldst_host(env, ldst_host, vd, evl, env->vstart, host,
- esz, is_load);
+ vext_continuous_ldst_host(env, ldst_host, vd, evl, env->vstart,
+ host, esz, is_load);
} else {
for (i = env->vstart; i < evl; ++i) {
k = 0;
@@ -357,7 +357,7 @@ vext_page_ldst_us(CPURISCVState *env, void *vd,
target_ulong addr,
env->vstart += elems;
} else {
if (nf == 1) {
- vext_continus_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vstart,
+ vext_continuous_ldst_tlb(env, ldst_tlb, vd, evl, addr, env->vstart,
ra, esz, is_load);
} else {
/* load bytes from guest memory */
--
2.47.1
- [PULL 00/50] riscv-to-apply queue, Alistair Francis, 2025/01/17
- [PULL 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names,
Alistair Francis <=
- [PULL 02/50] target/riscv: rvv: speed up small unit-stride loads and stores, Alistair Francis, 2025/01/17
- [PULL 03/50] riscv/gdbstub: add V bit to priv reg, Alistair Francis, 2025/01/17
- [PULL 04/50] target/riscv: add shcounterenw, Alistair Francis, 2025/01/17
- [PULL 05/50] target/riscv: add shvstvala, Alistair Francis, 2025/01/17
- [PULL 06/50] target/riscv: add shtvala, Alistair Francis, 2025/01/17
- [PULL 07/50] target/riscv: add shvstvecd, Alistair Francis, 2025/01/17
- [PULL 08/50] target/riscv: add shvsatpa, Alistair Francis, 2025/01/17
- [PULL 09/50] target/riscv: add shgatpa, Alistair Francis, 2025/01/17
- [PULL 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/17
- [PULL 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/17