[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 07/48] intel_iommu: Make pasid entry type check accurate
From: |
Michael S. Tsirkin |
Subject: |
[PULL 07/48] intel_iommu: Make pasid entry type check accurate |
Date: |
Wed, 15 Jan 2025 13:08:47 -0500 |
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-3-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0ab1676d5f..bd639b7ff7 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -759,20 +759,16 @@ static inline bool vtd_pe_type_check(X86IOMMUState
*x86_iommu,
VTDPASIDEntry *pe)
{
switch (VTD_PE_GET_TYPE(pe)) {
- case VTD_SM_PASID_ENTRY_FLT:
case VTD_SM_PASID_ENTRY_SLT:
- case VTD_SM_PASID_ENTRY_NESTED:
- break;
+ return true;
case VTD_SM_PASID_ENTRY_PT:
- if (!x86_iommu->pt_supported) {
- return false;
- }
- break;
+ return x86_iommu->pt_supported;
+ case VTD_SM_PASID_ENTRY_FLT:
+ case VTD_SM_PASID_ENTRY_NESTED:
default:
/* Unknown type */
return false;
}
- return true;
}
static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)
--
MST
- [PULL 00/48] virtio,pc,pci: features, fixes, cleanups, Michael S. Tsirkin, 2025/01/15
- [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature, Michael S. Tsirkin, 2025/01/15
- [PULL 02/48] pci: ensure valid link status bits for downstream ports, Michael S. Tsirkin, 2025/01/15
- [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI, Michael S. Tsirkin, 2025/01/15
- [PULL 03/48] tests: acpi: whitelist expected blobs, Michael S. Tsirkin, 2025/01/15
- [PULL 05/48] tests: acpi: update expected blobs, Michael S. Tsirkin, 2025/01/15
- [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec, Michael S. Tsirkin, 2025/01/15
- [PULL 07/48] intel_iommu: Make pasid entry type check accurate,
Michael S. Tsirkin <=
- [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 11/48] intel_iommu: Implement stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 10/48] intel_iommu: Rename slpte to pte, Michael S. Tsirkin, 2025/01/15
- [PULL 12/48] intel_iommu: Check if the input address is canonical, Michael S. Tsirkin, 2025/01/15
- [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range, Michael S. Tsirkin, 2025/01/15
- [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes, Michael S. Tsirkin, 2025/01/15
- [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table, Michael S. Tsirkin, 2025/01/15
- [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument, Michael S. Tsirkin, 2025/01/15