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[PULL 02/48] pci: ensure valid link status bits for downstream ports
From: |
Michael S. Tsirkin |
Subject: |
[PULL 02/48] pci: ensure valid link status bits for downstream ports |
Date: |
Wed, 15 Jan 2025 13:08:32 -0500 |
From: Sebastian Ott <sebott@redhat.com>
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport 0000:08:01.0: pciehp: Slot(2): Card present
pcieport 0000:08:01.0: pciehp: Slot(2): Link Up
pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000
There's 2 cases where LNKSTA isn't setup properly:
* the downstream device has no express capability
* max link width of the bridge is 0
Move the sanity checks added via 88c869198aa63
("pci: Sanity test minimum downstream LNKSTA") outside of the
branch to make sure downstream ports always have a valid LNKSTA.
Signed-off-by: Sebastian Ott <sebott@redhat.com>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-Id: <20241203121928.14861-1-sebott@redhat.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/pci/pcie.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 0b455c8654..1b12db6fa2 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -1113,18 +1113,22 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
if ((lnksta & PCI_EXP_LNKSTA_NLW) > (lnkcap & PCI_EXP_LNKCAP_MLW)) {
lnksta &= ~PCI_EXP_LNKSTA_NLW;
lnksta |= lnkcap & PCI_EXP_LNKCAP_MLW;
- } else if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
- lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
}
if ((lnksta & PCI_EXP_LNKSTA_CLS) > (lnkcap & PCI_EXP_LNKCAP_SLS)) {
lnksta &= ~PCI_EXP_LNKSTA_CLS;
lnksta |= lnkcap & PCI_EXP_LNKCAP_SLS;
- } else if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
- lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
}
}
+ if (!(lnksta & PCI_EXP_LNKSTA_NLW)) {
+ lnksta |= QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1);
+ }
+
+ if (!(lnksta & PCI_EXP_LNKSTA_CLS)) {
+ lnksta |= QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT);
+ }
+
pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, lnksta &
--
MST
- [PULL 00/48] virtio,pc,pci: features, fixes, cleanups, Michael S. Tsirkin, 2025/01/15
- [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature, Michael S. Tsirkin, 2025/01/15
- [PULL 02/48] pci: ensure valid link status bits for downstream ports,
Michael S. Tsirkin <=
- [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI, Michael S. Tsirkin, 2025/01/15
- [PULL 03/48] tests: acpi: whitelist expected blobs, Michael S. Tsirkin, 2025/01/15
- [PULL 05/48] tests: acpi: update expected blobs, Michael S. Tsirkin, 2025/01/15
- [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec, Michael S. Tsirkin, 2025/01/15
- [PULL 07/48] intel_iommu: Make pasid entry type check accurate, Michael S. Tsirkin, 2025/01/15
- [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 11/48] intel_iommu: Implement stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 10/48] intel_iommu: Rename slpte to pte, Michael S. Tsirkin, 2025/01/15
- [PULL 12/48] intel_iommu: Check if the input address is canonical, Michael S. Tsirkin, 2025/01/15