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[PATCH v2 42/81] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
From: |
Richard Henderson |
Subject: |
[PATCH v2 42/81] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 |
Date: |
Tue, 7 Jan 2025 00:00:33 -0800 |
Extracts which abut bit 32 may use 32-bit shifts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-has.h | 24 +++++++-----------------
tcg/riscv/tcg-target.c.inc | 16 ++++++++++++----
2 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 5bf62c7c7f..e890546c3a 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -112,31 +112,21 @@
static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
- if (ofs == 0) {
- switch (len) {
- case 16:
- return cpuinfo & CPUINFO_ZBB;
- case 32:
- return (cpuinfo & CPUINFO_ZBA) && type == TCG_TYPE_I64;
- }
+ if (type == TCG_TYPE_I64 && ofs + len == 32) {
+ /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
+ return ofs || (cpuinfo & CPUINFO_ZBA);
}
- return false;
+ return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16;
}
#define TCG_TARGET_extract_valid tcg_target_extract_valid
static inline bool
tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
{
- if (ofs == 0) {
- switch (len) {
- case 8:
- case 16:
- return cpuinfo & CPUINFO_ZBB;
- case 32:
- return type == TCG_TYPE_I64;
- }
+ if (type == TCG_TYPE_I64 && ofs + len == 32) {
+ return true;
}
- return false;
+ return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
}
#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index fc93900c6d..4f6e18f59e 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2344,8 +2344,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
break;
case INDEX_op_extract_i64:
- if (a2 == 0 && args[3] == 32) {
- tcg_out_ext32u(s, a0, a1);
+ if (a2 + args[3] == 32) {
+ if (a2 == 0) {
+ tcg_out_ext32u(s, a0, a1);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
+ }
break;
}
/* FALLTHRU */
@@ -2358,8 +2362,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGType type,
break;
case INDEX_op_sextract_i64:
- if (a2 == 0 && args[3] == 32) {
- tcg_out_ext32s(s, a0, a1);
+ if (a2 + args[3] == 32) {
+ if (a2 == 0) {
+ tcg_out_ext32s(s, a0, a1);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
+ }
break;
}
/* FALLTHRU */
--
2.43.0
- Re: [PATCH v2 47/81] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}, (continued)
- [PATCH v2 48/81] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}, Richard Henderson, 2025/01/07
- [PATCH v2 59/81] tcg: Merge INDEX_op_andc_{i32,i64}, Richard Henderson, 2025/01/07
- [PATCH v2 58/81] tcg: Convert andc to TCGOutOpBinary, Richard Henderson, 2025/01/07
- [PATCH v2 42/81] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64,
Richard Henderson <=
- [PATCH v2 64/81] tcg: Merge INDEX_op_orc_{i32,i64}, Richard Henderson, 2025/01/07
- [PATCH v2 70/81] tcg: Convert nand to TCGOutOpBinary, Richard Henderson, 2025/01/07
- [PATCH v2 73/81] tcg: Convert nor to TCGOutOpBinary, Richard Henderson, 2025/01/07
- [PATCH v2 40/81] tcg/ppc: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/07
- [PATCH v2 43/81] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/07
- [PATCH v2 50/81] tcg: Add all_outop[], Richard Henderson, 2025/01/07