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[PATCH 36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extrac
From: |
Richard Henderson |
Subject: |
[PATCH 36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract |
Date: |
Thu, 2 Jan 2025 10:06:16 -0800 |
Accept AND, ext32u, ext32s extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-has.h | 26 ++++++++++++++++++++++----
tcg/mips/tcg-target.c.inc | 33 ++++++++++++++++++++++++++++++---
2 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index d01f74a48f..2932f99a97 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -71,8 +71,8 @@ extern bool use_mips32r2_instructions;
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
-#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
@@ -80,8 +80,8 @@ extern bool use_mips32r2_instructions;
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
-#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 1
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
@@ -99,4 +99,22 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0
+#define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions
+
+static inline bool
+tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
+{
+ if (ofs == 0) {
+ switch (len) {
+ case 8:
+ case 16:
+ return use_mips32r2_instructions;
+ case 32:
+ return type == TCG_TYPE_I64;
+ }
+ }
+ return false;
+}
+#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
+
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 8857398893..6acc2c99a4 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2041,12 +2041,37 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
args[3] + args[4] - 1, args[3]);
break;
+
case INDEX_op_extract_i32:
- tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
+ if (a2 == 0 && args[3] <= 16) {
+ tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
+ } else {
+ tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
+ }
break;
case INDEX_op_extract_i64:
- tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
- args[3] - 1, a2);
+ if (a2 == 0 && args[3] <= 16) {
+ tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
+ } else {
+ tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
+ a0, a1, args[3] - 1, a2);
+ }
+ break;
+
+ case INDEX_op_sextract_i64:
+ if (a2 == 0 && args[3] == 32) {
+ tcg_out_ext32s(s, a0, a1);
+ break;
+ }
+ /* FALLTHRU */
+ case INDEX_op_sextract_i32:
+ if (a2 == 0 && args[3] == 8) {
+ tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1);
+ } else if (a2 == 0 && args[3] == 16) {
+ tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1);
+ } else {
+ g_assert_not_reached();
+ }
break;
case INDEX_op_brcond_i32:
@@ -2169,6 +2194,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_ext8s_i32:
case INDEX_op_ext16s_i32:
case INDEX_op_extract_i32:
+ case INDEX_op_sextract_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64:
@@ -2190,6 +2216,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
+ case INDEX_op_sextract_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
--
2.43.0
- Re: [PATCH 27/73] tcg: Merge TCG_TARGET_HAS_{muls2, mulu2, mulsh, muluh}, (continued)
- [PATCH 12/73] target/i386: Remove TCG_TARGET_extract_tl_valid, Richard Henderson, 2025/01/02
- [PATCH 30/73] tcg/i386: Handle all 8-bit extensions for i686, Richard Henderson, 2025/01/02
- [PATCH 25/73] tcg: Merge TCG_TARGET_HAS_rot_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 26/73] tcg: Merge TCG_TARGET_HAS_{clz,ctz,ctpop}, Richard Henderson, 2025/01/02
- [PATCH 29/73] tcg: Merge TCG_TARGET_HAS_negsetcond_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 34/73] tcg/arm: Add full [US]XT[BH] into {s}extract, Richard Henderson, 2025/01/02
- [PATCH 36/73] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract,
Richard Henderson <=
- [PATCH 39/73] tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64, Richard Henderson, 2025/01/02
- [PATCH 40/73] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/02
- [PATCH 52/73] tcg: Use tcg_op_supported in process_op_defs, Richard Henderson, 2025/01/02
- [PATCH 57/73] tcg: Add TCGType argument to tcg_out_op, Richard Henderson, 2025/01/02
- [PATCH 55/73] tcg: Merge INDEX_op_{ld,st}*_{i32_i64}, Richard Henderson, 2025/01/02
- [PATCH 58/73] tcg/optimize: Remove OptContext.type, Richard Henderson, 2025/01/02
- [PATCH 67/73] tcg: Merge extract, sextract operations, Richard Henderson, 2025/01/02
- [PATCH 41/73] tcg/sparc64: Use SRA, SRL for {s}extract_i64, Richard Henderson, 2025/01/02
- [PATCH 42/73] tcg/tci: Provide TCG_TARGET_{s}extract_valid, Richard Henderson, 2025/01/02