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[PATCH 06/10] target/riscv: Add `ext_smdbltrp` in RISCVCPUConfig.
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From: |
Clément Léger |
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Subject: |
[PATCH 06/10] target/riscv: Add `ext_smdbltrp` in RISCVCPUConfig. |
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Date: |
Thu, 12 Sep 2024 10:48:25 +0200 |
This variable is used to determine if the Smdbltrp extension is enabled.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index dd804f95d4..4c4caa2b39 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -78,6 +78,7 @@ struct RISCVCPUConfig {
bool ext_sstc;
bool ext_smcntrpmf;
bool ext_ssdbltrp;
+ bool ext_smdbltrp;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.45.2
- [PATCH 00/10] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2024/09/12
- [PATCH 01/10] target/riscv: Add `ext_ssdbltrp` in RISCVCPUConfig., Clément Léger, 2024/09/12
- [PATCH 02/10] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2024/09/12
- [PATCH 04/10] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2024/09/12
- [PATCH 03/10] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2024/09/12
- [PATCH 05/10] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2024/09/12
- [PATCH 08/10] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Clément Léger, 2024/09/12
- [PATCH 09/10] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2024/09/12
- [PATCH 06/10] target/riscv: Add `ext_smdbltrp` in RISCVCPUConfig.,
Clément Léger <=
- [PATCH 10/10] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2024/09/12
- [PATCH 07/10] target/riscv: Add Smdbltrp CSRs handling, Clément Léger, 2024/09/12