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[PULL 44/47] target: riscv: Add Svvptc extension support
From: |
Alistair Francis |
Subject: |
[PULL 44/47] target: riscv: Add Svvptc extension support |
Date: |
Thu, 12 Sep 2024 15:29:49 +1000 |
From: Alexandre Ghiti <alexghiti@rivosinc.com>
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 96fe26d4ea..355afedfd3 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -81,6 +81,7 @@ struct RISCVCPUConfig {
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
+ bool ext_svvptc;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d215681905..cb675f0278 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -197,6 +197,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -1520,6 +1521,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+ MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
--
2.46.0
- [PULL 34/47] bsd-user: Add RISC-V thread setup and initialization support, (continued)
- [PULL 34/47] bsd-user: Add RISC-V thread setup and initialization support, Alistair Francis, 2024/09/12
- [PULL 46/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled, Alistair Francis, 2024/09/12
- [PULL 43/47] hw/riscv: Respect firmware ELF entry point, Alistair Francis, 2024/09/12
- [PULL 39/47] bsd-user: Implement RISC-V signal trampoline setup functions, Alistair Francis, 2024/09/12
- [PULL 37/47] bsd-user: Add generic RISC-V64 target definitions, Alistair Francis, 2024/09/12
- [PULL 40/47] bsd-user: Implement 'get_mcontext' for RISC-V, Alistair Francis, 2024/09/12
- [PULL 45/47] target/riscv32: Fix masking of physical address, Alistair Francis, 2024/09/12
- [PULL 47/47] hw/intc: riscv-imsic: Fix interrupt state updates., Alistair Francis, 2024/09/12
- [PULL 42/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Alistair Francis, 2024/09/12
- [PULL 41/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Alistair Francis, 2024/09/12
- [PULL 44/47] target: riscv: Add Svvptc extension support,
Alistair Francis <=
- Re: [PULL 00/47] riscv-to-apply queue, Peter Maydell, 2024/09/13