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Re: [PATCH v11 17/20] target/riscv: compressed encodings for sspush and
From: |
Alistair Francis |
Subject: |
Re: [PATCH v11 17/20] target/riscv: compressed encodings for sspush and sspopchk |
Date: |
Thu, 29 Aug 2024 10:03:36 +1000 |
On Thu, Aug 29, 2024 at 3:50 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> sspush/sspopchk have compressed encodings carved out of zcmops.
> compressed sspush is designated as c.mop.1 while compressed sspopchk
> is designated as c.mop.5.
>
> Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
> c.sspopchk x5 exists while c.sspopchk x1 doesn't.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Co-developed-by: Jim Shu <jim.shu@sifive.com>
> Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn16.decode | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 3953bcf82d..bf893d1c2e 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -140,6 +140,10 @@ sw 110 ... ... .. ... 00 @cs_w
> addi 000 . ..... ..... 01 @ci
> addi 010 . ..... ..... 01 @c_li
> {
> + # c.sspush x1 carving out of zcmops
> + sspush 011 0 00001 00000 01 &r2_s rs2=1 rs1=0
> + # c.sspopchk x5 carving out of zcmops
> + sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0
> c_mop_n 011 0 0 n:3 1 00000 01
> illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
> addi 011 . 00010 ..... 01 @c_addi16sp
> --
> 2.44.0
>
>
- [PATCH v11 10/20] target/riscv: Add zicfiss extension, (continued)
[PATCH v11 14/20] target/riscv: AMO operations always raise store/AMO fault, Deepak Gupta, 2024/08/28
[PATCH v11 17/20] target/riscv: compressed encodings for sspush and sspopchk, Deepak Gupta, 2024/08/28
- Re: [PATCH v11 17/20] target/riscv: compressed encodings for sspush and sspopchk,
Alistair Francis <=
[PATCH v11 13/20] target/riscv: mmu changes for zicfiss shadow stack protection, Deepak Gupta, 2024/08/28
[PATCH v11 18/20] disas/riscv: enable disassembly for zicfiss instructions, Deepak Gupta, 2024/08/28
[PATCH v11 20/20] target/riscv: Expose zicfiss extension as a cpu property, Deepak Gupta, 2024/08/28
[PATCH v11 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/28