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[PULL 19/21] hw/arm : Create Bl475eMachineState
From: |
Peter Maydell |
Subject: |
[PULL 19/21] hw/arm : Create Bl475eMachineState |
Date: |
Tue, 30 Apr 2024 17:48:40 +0100 |
From: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 14 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index d862aa43fc3..970c637ce61 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -2,8 +2,8 @@
* B-L475E-IOT01A Discovery Kit machine
* (B-L475E-IOT01A IoT Node)
*
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
@@ -32,33 +32,51 @@
/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
-static void b_l475e_iot01a_init(MachineState *machine)
+#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
+OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
+
+typedef struct Bl475eMachineState {
+ MachineState parent_obj;
+
+ Stm32l4x5SocState soc;
+} Bl475eMachineState;
+
+static void bl475e_init(MachineState *machine)
{
+ Bl475eMachineState *s = B_L475E_IOT01A(machine);
const Stm32l4x5SocClass *sc;
- DeviceState *dev;
- dev = qdev_new(TYPE_STM32L4X5XG_SOC);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_STM32L4X5XG_SOC);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
- sc = STM32L4X5_SOC_GET_CLASS(dev);
- armv7m_load_kernel(ARM_CPU(first_cpu),
- machine->kernel_filename,
- 0, sc->flash_size);
+ sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
+ sc->flash_size);
}
-static void b_l475e_iot01a_machine_init(MachineClass *mc)
+static void bl475e_machine_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
static const char *machine_valid_cpu_types[] = {
ARM_CPU_TYPE_NAME("cortex-m4"),
NULL
};
mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
- mc->init = b_l475e_iot01a_init;
+ mc->init = bl475e_init;
mc->valid_cpu_types = machine_valid_cpu_types;
/* SRAM pre-allocated as part of the SoC instantiation */
mc->default_ram_size = 0;
}
-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
+static const TypeInfo bl475e_machine_type[] = {
+ {
+ .name = TYPE_B_L475E_IOT01A,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(Bl475eMachineState),
+ .class_init = bl475e_machine_init,
+ }
+};
+
+DEFINE_TYPES(bl475e_machine_type)
--
2.34.1
- [PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max, (continued)
- [PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max, Peter Maydell, 2024/04/30
- [PULL 01/21] hw/core/clock: allow clock_propagate on child clocks, Peter Maydell, 2024/04/30
- [PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features, Peter Maydell, 2024/04/30
- [PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16, Peter Maydell, 2024/04/30
- [PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz, Peter Maydell, 2024/04/30
- [PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property, Peter Maydell, 2024/04/30
- [PULL 10/21] target/arm: Refactor default generic timer frequency handling, Peter Maydell, 2024/04/30
- [PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1, Peter Maydell, 2024/04/30
- [PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian, Peter Maydell, 2024/04/30
- [PULL 18/21] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC, Peter Maydell, 2024/04/30
- [PULL 19/21] hw/arm : Create Bl475eMachineState,
Peter Maydell <=
- [PULL 14/21] hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields, Peter Maydell, 2024/04/30
- [PULL 13/21] target/arm: Default to 1GHz cntfrq for 'max' and new CPUs, Peter Maydell, 2024/04/30
- [PULL 20/21] hw/arm : Connect DM163 to B-L475E-IOT01A, Peter Maydell, 2024/04/30
- [PULL 17/21] hw/display : Add device DM163, Peter Maydell, 2024/04/30
- [PULL 21/21] tests/qtest : Add testcase for DM163, Peter Maydell, 2024/04/30
- [PULL 15/21] hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size, Peter Maydell, 2024/04/30
- Re: [PULL 00/21] target-arm queue, Richard Henderson, 2024/04/30