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[PATCH v10 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_
From: |
Zhao Liu |
Subject: |
[PATCH v10 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() |
Date: |
Thu, 21 Mar 2024 22:40:35 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores and cs->nr_threads do not accurately
represent its meaning, the use of cs->nr_cores or cs->nr_threads is
prone to confusion and mistakes.
And the structure X86CPUTopoInfo names its members clearly, thus the
variable "topo_info" should be preferred.
In addition, in cpu_x86_cpuid(), to uniformly use the topology variable,
replace env->dies with topo_info.dies_per_pkg as well.
Suggested-by: Robert Hoo <robert.hu@linux.intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Babu Moger <babu.moger@amd.com>
---
Changes since v9:
* Polished the commit message. ( Xiaoyao)
Changes since v8:
* Added Philippe's reviewed-by tag.
Changes since v7:
* Renamed cpus_per_pkg to threads_per_pkg. (Xiaoyao)
* Dropped Michael/Babu's Acked/Tested tags since the code change.
* Re-added Yongwei's Tested tag For his re-testing.
* Added Xiaoyao's Reviewed tag.
Changes since v3:
* Fixed typo. (Babu)
Changes since v1:
* Extracted cores_per_socket from the code block and use it as a local
variable for cpu_x86_cpuid(). (Yanan)
* Removed vcpus_per_socket variable and use cpus_per_pkg directly.
(Yanan)
* Replaced env->dies with topo_info.dies_per_pkg in cpu_x86_cpuid().
---
target/i386/cpu.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8f559b42f706..0ad400cd709a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6017,11 +6017,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
uint32_t limit;
uint32_t signature[3];
X86CPUTopoInfo topo_info;
+ uint32_t cores_per_pkg;
+ uint32_t threads_per_pkg;
topo_info.dies_per_pkg = env->nr_dies;
topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
topo_info.threads_per_core = cs->nr_threads;
+ cores_per_pkg = topo_info.cores_per_die * topo_info.dies_per_pkg;
+ threads_per_pkg = cores_per_pkg * topo_info.threads_per_core;
+
/* Calculate & apply limits for different index ranges */
if (index >= 0xC0000000) {
limit = env->cpuid_xlevel2;
@@ -6057,8 +6062,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_EXT_OSXSAVE;
}
*edx = env->features[FEAT_1_EDX];
- if (cs->nr_cores * cs->nr_threads > 1) {
- *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
+ if (threads_per_pkg > 1) {
+ *ebx |= threads_per_pkg << 16;
*edx |= CPUID_HT;
}
if (!cpu->enable_pmu) {
@@ -6106,15 +6111,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*/
if (*eax & 31) {
int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
- int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
- if (cs->nr_cores > 1) {
+
+ if (cores_per_pkg > 1) {
addressable_cores_width = apicid_pkg_offset(&topo_info) -
apicid_core_offset(&topo_info);
*eax &= ~0xFC000000;
*eax |= ((1 << addressable_cores_width) - 1) << 26;
}
- if (host_vcpus_per_cache > vcpus_per_socket) {
+ if (host_vcpus_per_cache > threads_per_pkg) {
/* Share the cache at package level. */
addressable_threads_width = apicid_pkg_offset(&topo_info);
@@ -6260,12 +6265,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
- *ebx = cs->nr_threads;
+ *ebx = topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_pkg_offset(&topo_info);
- *ebx = cs->nr_cores * cs->nr_threads;
+ *ebx = threads_per_pkg;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
default:
@@ -6285,7 +6290,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
case 0x1F:
/* V2 Extended Topology Enumeration Leaf */
- if (env->nr_dies < 2) {
+ if (topo_info.dies_per_pkg < 2) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
@@ -6295,7 +6300,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
switch (count) {
case 0:
*eax = apicid_core_offset(&topo_info);
- *ebx = cs->nr_threads;
+ *ebx = topo_info.threads_per_core;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
@@ -6305,7 +6310,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
case 2:
*eax = apicid_pkg_offset(&topo_info);
- *ebx = cs->nr_cores * cs->nr_threads;
+ *ebx = threads_per_pkg;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
default:
@@ -6533,7 +6538,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
* discards multiple thread information if it is set.
* So don't set it here for Intel to make Linux guests happy.
*/
- if (cs->nr_cores * cs->nr_threads > 1) {
+ if (threads_per_pkg > 1) {
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
@@ -6599,7 +6604,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*eax |= (cpu_x86_virtual_addr_width(env) << 8);
}
*ebx = env->features[FEAT_8000_0008_EBX];
- if (cs->nr_cores * cs->nr_threads > 1) {
+ if (threads_per_pkg > 1) {
/*
* Bits 15:12 is "The number of bits in the initial
* Core::X86::Apic::ApicId[ApicId] value that indicate
@@ -6607,7 +6612,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
* Bits 7:0 is "The number of threads in the package is NC+1"
*/
*ecx = (apicid_pkg_offset(&topo_info) << 12) |
- ((cs->nr_cores * cs->nr_threads) - 1);
+ (threads_per_pkg - 1);
} else {
*ecx = 0;
}
--
2.34.1
- [PATCH v10 00/21] i386: Introduce smp.modules and clean up cache topology, Zhao Liu, 2024/03/21
- [PATCH v10 01/21] hw/core/machine: Introduce the module as a CPU topology level, Zhao Liu, 2024/03/21
- [PATCH v10 02/21] hw/core/machine: Support modules in -smp, Zhao Liu, 2024/03/21
- [PATCH v10 03/21] hw/core: Introduce module-id as the topology subindex, Zhao Liu, 2024/03/21
- [PATCH v10 04/21] hw/core: Support module-id in numa configuration, Zhao Liu, 2024/03/21
- [PATCH v10 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2024/03/21
- [PATCH v10 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4], Zhao Liu, 2024/03/21
- [PATCH v10 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2024/03/21
- [PATCH v10 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(),
Zhao Liu <=
- [PATCH v10 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels, Zhao Liu, 2024/03/21
- [PATCH v10 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/03/21
- [PATCH v10 12/21] i386: Introduce module level cpu topology to CPUX86State, Zhao Liu, 2024/03/21
- [PATCH v10 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2024/03/21
- [PATCH v10 13/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2024/03/21
- [PATCH v10 14/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2024/03/21
- [PATCH v10 17/21] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2024/03/21
- [PATCH v10 15/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2024/03/21
- [PATCH v10 18/21] hw/i386/pc: Support smp.modules for x86 PC machine, Zhao Liu, 2024/03/21
- [PATCH v10 16/21] i386/cpu: Introduce module-id to X86CPU, Zhao Liu, 2024/03/21