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[PATCH v10 01/21] hw/core/machine: Introduce the module as a CPU topolog
From: |
Zhao Liu |
Subject: |
[PATCH v10 01/21] hw/core/machine: Introduce the module as a CPU topology level |
Date: |
Thu, 21 Mar 2024 22:40:28 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
In x86, module is the topology level above core, which contains a set
of cores that share certain resources (in current products, the resource
usually includes L2 cache, as well as module scoped features and MSRs).
Though smp.clusters could also share the L2 cache resource [1], there
are following reasons that drive us to introduce the new smp.modules:
* As the CPU topology abstraction in device tree [2], cluster supports
nesting (though currently QEMU hasn't support that). In contrast,
(x86) module does not support nesting.
* Due to nesting, there is great flexibility in sharing resources
on cluster, rather than narrowing cluster down to sharing L2 (and
L3 tags) as the lowest topology level that contains cores.
* Flexible nesting of cluster allows it to correspond to any level
between the x86 package and core.
* In Linux kernel, x86's cluster only represents the L2 cache domain
but QEMU's smp.clusters is the CPU topology level. Linux kernel will
also expose module level topology information in sysfs for x86. To
avoid cluster ambiguity and keep a consistent CPU topology naming
style with the Linux kernel, we introduce module level for x86.
The module is, in existing hardware practice, the lowest layer that
contains the core, while the cluster is able to have a higher
topological scope than the module due to its nesting.
Therefore, place the module between the cluster and the core:
drawer/book/socket/die/cluster/module/core/thread
With the above topological hierarchy order, introduce module level
support in MachineState and MachineClass.
[1]:
https://lore.kernel.org/qemu-devel/c3d68005-54e0-b8fe-8dc1-5989fe3c7e69@huawei.com/
[2]:
https://www.kernel.org/doc/Documentation/devicetree/bindings/cpu/cpu-topology.txt
Suggested-by: Xiaoyao Li <xiaoyao.li@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
---
Changes since v8:
* Add the reason of why a new module level is needed in commit message.
(Markus).
* Add the description about how Linux kernel supports x86 module level.
(Daniel)
Changes since v7:
* New commit to introduce module level in -smp.
---
hw/core/machine-smp.c | 2 +-
hw/core/machine.c | 1 +
include/hw/boards.h | 4 ++++
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 27864c950766..2e68fcfdfd79 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -266,7 +266,7 @@ void machine_parse_smp_config(MachineState *ms,
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
{
- return ms->smp.cores * ms->smp.clusters * ms->smp.dies;
+ return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies;
}
unsigned int machine_topo_get_threads_per_socket(const MachineState *ms)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 37ede0e7d4fd..fe0579b7a7e9 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1154,6 +1154,7 @@ static void machine_initfn(Object *obj)
ms->smp.sockets = 1;
ms->smp.dies = 1;
ms->smp.clusters = 1;
+ ms->smp.modules = 1;
ms->smp.cores = 1;
ms->smp.threads = 1;
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 8b8f6d5c00d3..392be94f3cd7 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -143,6 +143,7 @@ typedef struct {
* provided SMP configuration
* @books_supported - whether books are supported by the machine
* @drawers_supported - whether drawers are supported by the machine
+ * @modules_supported - whether modules are supported by the machine
*/
typedef struct {
bool prefer_sockets;
@@ -151,6 +152,7 @@ typedef struct {
bool has_clusters;
bool books_supported;
bool drawers_supported;
+ bool modules_supported;
} SMPCompatProps;
/**
@@ -338,6 +340,7 @@ typedef struct DeviceMemoryState {
* @sockets: the number of sockets in one book
* @dies: the number of dies in one socket
* @clusters: the number of clusters in one die
+ * @modules: the number of modules in one cluster
* @cores: the number of cores in one cluster
* @threads: the number of threads in one core
* @max_cpus: the maximum number of logical processors on the machine
@@ -349,6 +352,7 @@ typedef struct CpuTopology {
unsigned int sockets;
unsigned int dies;
unsigned int clusters;
+ unsigned int modules;
unsigned int cores;
unsigned int threads;
unsigned int max_cpus;
--
2.34.1
- [PATCH v10 00/21] i386: Introduce smp.modules and clean up cache topology, Zhao Liu, 2024/03/21
- [PATCH v10 01/21] hw/core/machine: Introduce the module as a CPU topology level,
Zhao Liu <=
- [PATCH v10 02/21] hw/core/machine: Support modules in -smp, Zhao Liu, 2024/03/21
- [PATCH v10 03/21] hw/core: Introduce module-id as the topology subindex, Zhao Liu, 2024/03/21
- [PATCH v10 04/21] hw/core: Support module-id in numa configuration, Zhao Liu, 2024/03/21
- [PATCH v10 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU, Zhao Liu, 2024/03/21
- [PATCH v10 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4], Zhao Liu, 2024/03/21
- [PATCH v10 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2024/03/21
- [PATCH v10 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2024/03/21
- [PATCH v10 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels, Zhao Liu, 2024/03/21
- [PATCH v10 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/03/21
- [PATCH v10 12/21] i386: Introduce module level cpu topology to CPUX86State, Zhao Liu, 2024/03/21