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[PATCH 01/10] qtest/phb4: Add testbench for PHB4
From: |
Saif Abrar |
Subject: |
[PATCH 01/10] qtest/phb4: Add testbench for PHB4 |
Date: |
Thu, 21 Mar 2024 05:04:13 -0500 |
New qtest TB added for PHB4.
TB reads PHB Version register and asserts that
bits[24:31] have value 0xA5.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
---
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 74 +++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 tests/qtest/pnv-phb4-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 36c5c13a7b..4795e51c17 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -168,6 +168,7 @@ qtests_ppc64 = \
(config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) +
\
(config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) +
\
(config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : [])
+ \
+ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) +
\
(config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) +
\
(slirp.found() ? ['pxe-test'] : []) + \
(config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : [])
+ \
diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c
new file mode 100644
index 0000000000..e3b809e9c4
--- /dev/null
+++ b/tests/qtest/pnv-phb4-test.c
@@ -0,0 +1,74 @@
+/*
+ * QTest testcase for PowerNV PHB4
+ *
+ * Copyright (c) 2024, IBM Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "hw/pci-host/pnv_phb4_regs.h"
+
+#define P10_XSCOM_BASE 0x000603fc00000000ull
+#define PHB4_MMIO 0x000600c3c0000000ull
+#define PHB4_XSCOM 0x8010900ull
+
+#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
+#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
+
+static uint64_t pnv_xscom_addr(uint32_t pcba)
+{
+ return P10_XSCOM_BASE | ((uint64_t) pcba << 3);
+}
+
+static uint64_t pnv_phb4_xscom_addr(uint32_t reg)
+{
+ return pnv_xscom_addr(PHB4_XSCOM + reg);
+}
+
+/*
+ * XSCOM read/write is indirect in PHB4:
+ * Write 'SCOM - HV Indirect Address Register'
+ * with register-offset to read/write.
+ - bit[0]: Valid Bit
+ - bit[51:61]: Indirect Address(00:10)
+ * Read/write 'SCOM - HV Indirect Data Register' to get/set the value.
+ */
+
+static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg)
+{
+ qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR),
+ PPC_BIT(0) | reg);
+ return qtest_readq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA));
+}
+
+/* Assert that 'PHB - Version Register Offset 0x0800' bits-[24:31] are 0xA5 */
+static void phb4_version_test(QTestState *qts)
+{
+ uint64_t ver = pnv_phb4_xscom_read(qts, PHB_VERSION);
+
+ /* PHB Version register [24:31]: Major Revision ID 0xA5 */
+ ver = ver >> (63 - 31);
+ g_assert_cmpuint(ver, ==, 0xA5);
+}
+
+static void test_phb4(void)
+{
+ QTestState *qts = NULL;
+
+ qts = qtest_initf("-machine powernv10 -accel tcg -nographic -d unimp");
+
+ /* Make sure test is running on PHB */
+ phb4_version_test(qts);
+
+ qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+ qtest_add_func("phb4", test_phb4);
+ return g_test_run();
+}
--
2.39.3
- [PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5, Saif Abrar, 2024/03/21
- [PATCH 07/10] pnv/phb4: Set link speed and width in the DLP training control register, Saif Abrar, 2024/03/21
- [PATCH 08/10] pnv/phb4: Implement IODA PCT table, Saif Abrar, 2024/03/21
- [PATCH 04/10] pnv/phb4: Implement read-only and write-only bits of registers, Saif Abrar, 2024/03/21
- [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts, Saif Abrar, 2024/03/21
- [PATCH 02/10] pnv/phb4: Add reset logic to PHB4, Saif Abrar, 2024/03/21
- [PATCH 05/10] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read, Saif Abrar, 2024/03/21
- [PATCH 09/10] hw/pci: Set write-mask bits for PCIE Link-Control-2 register, Saif Abrar, 2024/03/21
- [PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers, Saif Abrar, 2024/03/21
- [PATCH 03/10] pnv/phb4: Implement sticky reset logic in PHB4, Saif Abrar, 2024/03/21
- [PATCH 01/10] qtest/phb4: Add testbench for PHB4,
Saif Abrar <=