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[PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5
From: |
Saif Abrar |
Subject: |
[PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5 |
Date: |
Thu, 21 Mar 2024 05:04:12 -0500 |
Hello,
This series updates the existing PHB4 model to the latest spec:
"Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00".
Updates include the following:
- implemented sticky reset logic
- implemented read-only, write-only, W1C and WxC logic
- return all 1's on read to unimplemented registers
- update PCIE registers for link status, speed and width
- implement IODA PCT debug table without any functionality
- set write-mask bits for PCIE Link-Control-2 register that is read/written by
PHB4
- update LSI Source-ID register based on small/big PHB number of interrupts
Also, a new testbench for PHB4 model is added that does XSCOM read/writes
to various registers of interest and verifies the values.
Regards.
Saif Abrar (10):
qtest/phb4: Add testbench for PHB4
pnv/phb4: Add reset logic to PHB4
pnv/phb4: Implement sticky reset logic in PHB4
pnv/phb4: Implement read-only and write-only bits of registers
pnv/phb4: Implement write-clear and return 1's on unimplemented reg read
pnv/phb4: Set link-active status in HPSTAT and LMR registers
pnv/phb4: Set link speed and width in the DLP training control register
pnv/phb4: Implement IODA PCT table
hw/pci: Set write-mask bits for PCIE Link-Control-2 register
pnv/phb4: Mask off LSI Source-ID based on number of interrupts
hw/pci-host/pnv_phb4.c | 601 ++++++++++++++++++++--
hw/pci/pcie.c | 6 +
include/hw/pci-host/pnv_phb4.h | 9 +
include/hw/pci-host/pnv_phb4_regs.h | 66 ++-
include/standard-headers/linux/pci_regs.h | 3 +
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 177 +++++++
7 files changed, 805 insertions(+), 58 deletions(-)
create mode 100644 tests/qtest/pnv-phb4-test.c
--
2.39.3
- [PATCH 00/10] pnv/phb4: Update PHB4 to the latest spec PH5,
Saif Abrar <=