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Re: [PATCH v2 1/2] target/ppc: Merge various fpu helpers
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From: |
Nicholas Piggin |
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Subject: |
Re: [PATCH v2 1/2] target/ppc: Merge various fpu helpers |
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Date: |
Wed, 20 Mar 2024 15:03:39 +1000 |
On Fri Mar 15, 2024 at 4:44 PM AEST, Chinmay Rath wrote:
> This patch merges the definitions of the following set of fpu helper methods,
> which are similar, using macros :
>
> 1. f{add, sub, mul, div}(s)
> 2. fre(s)
> 3. frsqrte(s)
>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
> ---
> target/ppc/fpu_helper.c | 221 +++++++++++-----------------------------
> 1 file changed, 62 insertions(+), 159 deletions(-)
>
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index 4b3dcad5d1..8d0cbe27e7 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -490,54 +490,12 @@ static void float_invalid_op_addsub(CPUPPCState *env,
> int flags,
> }
> }
>
> -/* fadd - fadd. */
> -float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
> +static inline void addsub_flags_handler(CPUPPCState *env, int flags,
> + uintptr_t ra)
> {
> - float64 ret = float64_add(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_addsub(env, flags, 1, GETPC());
> - }
> -
> - return ret;
> -}
> -
> -/* fadds - fadds. */
> -float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2)
> -{
> - float64 ret = float64r32_add(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_addsub(env, flags, 1, GETPC());
> - }
> - return ret;
> -}
> -
> -/* fsub - fsub. */
> -float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
> -{
> - float64 ret = float64_sub(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_addsub(env, flags, 1, GETPC());
> + float_invalid_op_addsub(env, flags, 1, ra);
> }
> -
> - return ret;
> -}
> -
> -/* fsubs - fsubs. */
> -float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2)
> -{
> - float64 ret = float64r32_sub(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_addsub(env, flags, 1, GETPC());
> - }
> - return ret;
> }
>
> static void float_invalid_op_mul(CPUPPCState *env, int flags,
> @@ -550,29 +508,11 @@ static void float_invalid_op_mul(CPUPPCState *env, int
> flags,
> }
> }
>
> -/* fmul - fmul. */
> -float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
> -{
> - float64 ret = float64_mul(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_mul(env, flags, 1, GETPC());
> - }
> -
> - return ret;
> -}
> -
> -/* fmuls - fmuls. */
> -float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2)
> +static inline void mul_flags_handler(CPUPPCState *env, int flags, uintptr_t
> ra)
> {
> - float64 ret = float64r32_mul(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_mul(env, flags, 1, GETPC());
> + float_invalid_op_mul(env, flags, 1, ra);
> }
> - return ret;
> }
>
> static void float_invalid_op_div(CPUPPCState *env, int flags,
> @@ -587,36 +527,14 @@ static void float_invalid_op_div(CPUPPCState *env, int
> flags,
> }
> }
>
> -/* fdiv - fdiv. */
> -float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
> -{
> - float64 ret = float64_div(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_div(env, flags, 1, GETPC());
> - }
> - if (unlikely(flags & float_flag_divbyzero)) {
> - float_zero_divide_excp(env, GETPC());
> - }
> -
> - return ret;
> -}
> -
> -/* fdivs - fdivs. */
> -float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2)
> +static inline void div_flags_handler(CPUPPCState *env, int flags, uintptr_t
> ra)
> {
> - float64 ret = float64r32_div(arg1, arg2, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_div(env, flags, 1, GETPC());
> + float_invalid_op_div(env, flags, 1, ra);
> }
> if (unlikely(flags & float_flag_divbyzero)) {
> - float_zero_divide_excp(env, GETPC());
> + float_zero_divide_excp(env, ra);
> }
> -
> - return ret;
> }
>
> static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
> @@ -812,81 +730,66 @@ float64 helper_##name(CPUPPCState *env, float64 arg)
> \
> FPU_FSQRT(FSQRT, float64_sqrt)
> FPU_FSQRT(FSQRTS, float64r32_sqrt)
>
> -/* fre - fre. */
> -float64 helper_fre(CPUPPCState *env, float64 arg)
> -{
> - /* "Estimate" the reciprocal with actual division. */
> - float64 ret = float64_div(float64_one, arg, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid_snan)) {
> - float_invalid_op_vxsnan(env, GETPC());
> - }
> - if (unlikely(flags & float_flag_divbyzero)) {
> - float_zero_divide_excp(env, GETPC());
> - /* For FPSCR.ZE == 0, the result is 1/2. */
> - ret = float64_set_sign(float64_half, float64_is_neg(arg));
> - }
> -
> - return ret;
> +#define FPU_FRE(name, op)
> \
> +float64 helper_##name(CPUPPCState *env, float64 arg)
> \
> +{
> \
> + /* "Estimate" the reciprocal with actual division. */
> \
> + float64 ret = op(float64_one, arg, &env->fp_status);
> \
> + int flags = get_float_exception_flags(&env->fp_status);
> \
> +
> \
> + if (unlikely(flags & float_flag_invalid_snan)) {
> \
> + float_invalid_op_vxsnan(env, GETPC());
> \
> + }
> \
> + if (unlikely(flags & float_flag_divbyzero)) {
> \
> + float_zero_divide_excp(env, GETPC());
> \
> + /* For FPSCR.ZE == 0, the result is 1/2. */
> \
> + ret = float64_set_sign(float64_half, float64_is_neg(arg));
> \
> + }
> \
> +
> \
> + return ret;
> \
> }
>
> -/* fres - fres. */
> -uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
> -{
> - /* "Estimate" the reciprocal with actual division. */
> - float64 ret = float64r32_div(float64_one, arg, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid_snan)) {
> - float_invalid_op_vxsnan(env, GETPC());
> - }
> - if (unlikely(flags & float_flag_divbyzero)) {
> - float_zero_divide_excp(env, GETPC());
> - /* For FPSCR.ZE == 0, the result is 1/2. */
> - ret = float64_set_sign(float64_half, float64_is_neg(arg));
> - }
> -
> - return ret;
> +#define FPU_FRSQRTE(name, op)
> \
> +float64 helper_##name(CPUPPCState *env, float64 arg)
> \
> +{
> \
> + /* "Estimate" the reciprocal with actual division. */
> \
> + float64 rets = float64_sqrt(arg, &env->fp_status);
> \
> + float64 retd = op(float64_one, rets, &env->fp_status);
> \
> + int flags = get_float_exception_flags(&env->fp_status);
> \
> +
> \
> + if (unlikely(flags & float_flag_invalid)) {
> \
> + float_invalid_op_sqrt(env, flags, 1, GETPC());
> \
> + }
> \
> + if (unlikely(flags & float_flag_divbyzero)) {
> \
> + /* Reciprocal of (square root of) zero. */
> \
> + float_zero_divide_excp(env, GETPC());
> \
> + }
> \
> +
> \
> + return retd;
> \
> }
>
> -/* frsqrte - frsqrte. */
> -float64 helper_frsqrte(CPUPPCState *env, float64 arg)
> -{
> - /* "Estimate" the reciprocal with actual division. */
> - float64 rets = float64_sqrt(arg, &env->fp_status);
> - float64 retd = float64_div(float64_one, rets, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_sqrt(env, flags, 1, GETPC());
> - }
> - if (unlikely(flags & float_flag_divbyzero)) {
> - /* Reciprocal of (square root of) zero. */
> - float_zero_divide_excp(env, GETPC());
> - }
> -
> - return retd;
> +#define FPU_HELPER(name, op, flags_handler)
> \
> +float64 helper_##name(CPUPPCState *env, float64 arg1, float64 arg2)
> \
> +{
> \
> + float64 ret = op(arg1, arg2, &env->fp_status);
> \
> + int flags = get_float_exception_flags(&env->fp_status);
> \
> + uintptr_t ra = GETPC();
> \
> + flags_handler(env, flags, ra);
> \
> + return ret;
> \
> }
>
> -/* frsqrtes - frsqrtes. */
> -float64 helper_frsqrtes(CPUPPCState *env, float64 arg)
> -{
> - /* "Estimate" the reciprocal with actual division. */
> - float64 rets = float64_sqrt(arg, &env->fp_status);
> - float64 retd = float64r32_div(float64_one, rets, &env->fp_status);
> - int flags = get_float_exception_flags(&env->fp_status);
> -
> - if (unlikely(flags & float_flag_invalid)) {
> - float_invalid_op_sqrt(env, flags, 1, GETPC());
> - }
> - if (unlikely(flags & float_flag_divbyzero)) {
> - /* Reciprocal of (square root of) zero. */
> - float_zero_divide_excp(env, GETPC());
> - }
> -
> - return retd;
> -}
> +FPU_FRE(fre, float64_div)
> +FPU_FRE(fres, float64r32_div)
> +FPU_FRSQRTE(frsqrte, float64_div)
> +FPU_FRSQRTE(frsqrtes, float64r32_div)
> +FPU_HELPER(fadd, float64_add, addsub_flags_handler)
> +FPU_HELPER(fadds, float64r32_add, addsub_flags_handler)
> +FPU_HELPER(fsub, float64_sub, addsub_flags_handler)
> +FPU_HELPER(fsubs, float64r32_sub, addsub_flags_handler)
> +FPU_HELPER(fmul, float64_mul, mul_flags_handler)
> +FPU_HELPER(fmuls, float64r32_mul, mul_flags_handler)
> +FPU_HELPER(fdiv, float64_div, div_flags_handler)
> +FPU_HELPER(fdivs, float64r32_div, div_flags_handler)
>
> /* fsel - fsel. */
> uint64_t helper_FSEL(uint64_t a, uint64_t b, uint64_t c)