Re: [RFC PATCH v5 06/22] target/arm: Add support for Non-maskable Interrupt

[Richard Henderson]

On 3/19/24 07:03, Peter Maydell wrote:
> On Thu, 29 Feb 2024 at 23:02, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> > On 2/29/24 03:10, Jinjie Ruan via wrote:
> > > +    bool new_state = ((env->cp15.hcr_el2 & HCR_VI) &&
> > > +                      (env->cp15.hcrx_el2 & HCRX_VINMI)) ||
> > > +                     ((env->cp15.hcr_el2 & HCR_VF) &&
> > > +                      (env->cp15.hcrx_el2 & HCRX_VFNMI)) ||
> > > +        (env->irq_line_state & CPU_INTERRUPT_VNMI);
> >
> > Because the GIC cannot signal an FIQ with superpriority, I think you should not 
> > include VF
> > && VFNMI in CPU_INTERRUPT_VNMI.
>
> The GIC can't, but a hypervisor can -- it just sets the
> VF and VFNMI bits if it wants one. (Architecturally, the CPU
> has a FIQ-with-superpriority, it's only the GIC that doesn't.)

Yes, I know.

The point was not to mix (irq from cpu or gic) with (fiq from cpu) so that we can 
correctly determine superpriority later.

Another way would have been to add an fiq-with-superpriority CPU_INTERRUPT bit, but since 
there's only one way to get that at present, I thought the extra bit was overkill.


r~