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[PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant
From: |
Nicholas Piggin |
Subject: |
[PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant |
Date: |
Wed, 13 Mar 2024 02:58:21 +1000 |
This allows different pa-features for powernv8/9/10.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aa9786e970..52d964f77a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -133,7 +133,7 @@ static int get_cpus_node(void *fdt)
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
-static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
+static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
PowerPCCPU *cpu = pc->threads[0];
CPUState *cs = CPU(cpu);
@@ -149,11 +149,6 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
uint32_t cpufreq = 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
int offset;
char *nodename;
int cpus_offset = get_cpus_node(fdt);
@@ -236,15 +231,14 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void
*fdt)
page_sizes_prop, page_sizes_prop_size)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features, sizeof(pa_features))));
-
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
servers_prop[i] = cpu_to_be32(pc->pir + i);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
+
+ return offset;
}
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
@@ -299,6 +293,17 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
return chip;
}
+/*
+ * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
+ * HTM is always enabled because TCG does implement HTM, it's just a
+ * degenerate implementation.
+ */
+static const uint8_t pa_features_207[] = { 24, 0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
+
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
@@ -311,8 +316,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip,
void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
/* Interrupt Control Presenters (ICP). One per core. */
pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
@@ -335,8 +344,12 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip,
void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
@@ -358,8 +371,12 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip,
void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
--
2.42.0
- [PULL 00/38] ppc-for-9.0-2 queue, Nicholas Piggin, 2024/03/12
- [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing, Nicholas Piggin, 2024/03/12
- [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/03/12
- [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/03/12
- [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips, Nicholas Piggin, 2024/03/12
- [PULL 05/38] target/ppc: POWER10 does not have transactional memory, Nicholas Piggin, 2024/03/12
- [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features, Nicholas Piggin, 2024/03/12
- [PULL 07/38] ppc/spapr: Remove copy-paste from pa-features, Nicholas Piggin, 2024/03/12
- [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9, Nicholas Piggin, 2024/03/12
- [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant,
Nicholas Piggin <=
- [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Nicholas Piggin, 2024/03/12
- [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines, Nicholas Piggin, 2024/03/12
- [PULL 13/38] docs: Deprecate the pseries-2.12 machines, Nicholas Piggin, 2024/03/12
- [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines, Nicholas Piggin, 2024/03/12
- [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core, Nicholas Piggin, 2024/03/12
- [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC, Nicholas Piggin, 2024/03/12
- [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree, Nicholas Piggin, 2024/03/12
- [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1, Nicholas Piggin, 2024/03/12
- [PULL 19/38] target/ppc: Readability improvements in exception handlers, Nicholas Piggin, 2024/03/12
- [PULL 20/38] target/ppc: Add gen_exception_err_nip() function, Nicholas Piggin, 2024/03/12