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Re: [PULL 00/14] target-arm queue
From: |
Peter Maydell |
Subject: |
Re: [PULL 00/14] target-arm queue |
Date: |
Sat, 9 Mar 2024 14:58:50 +0000 |
On Fri, 8 Mar 2024 at 15:50, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
>
> Merge tag 'pull-maintainer-updates-060324-1' of
> https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20240308
>
> for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
>
> target/arm: Move v7m-related code from cpu32.c into a separate file
> (2024-03-08 14:45:03 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Implement FEAT_ECV
> * STM32L4x5: Implement GPIO device
> * Fix 32-bit SMOPA
> * Refactor v7m related code from cpu32.c into its own file
> * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
- [PULL 05/14] target/arm: Implement new FEAT_ECV trap bits, (continued)
- [PULL 05/14] target/arm: Implement new FEAT_ECV trap bits, Peter Maydell, 2024/03/08
- [PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU, Peter Maydell, 2024/03/08
- [PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written, Peter Maydell, 2024/03/08
- [PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase, Peter Maydell, 2024/03/08
- [PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later, Peter Maydell, 2024/03/08
- [PULL 12/14] target/arm: Fix 32-bit SMOPA, Peter Maydell, 2024/03/08
- [PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions, Peter Maydell, 2024/03/08
- [PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC, Peter Maydell, 2024/03/08
- [PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file, Peter Maydell, 2024/03/08
- [PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO, Peter Maydell, 2024/03/08
- Re: [PULL 00/14] target-arm queue,
Peter Maydell <=