Re: [PATCH v2 0/9] Add AST2700 support

[Cédric Le Goater]

On 3/5/24 04:38, Jamin Lin wrote:
> > -----Original Message-----
> > From: Cédric Le Goater <clg@kaod.org>
> > Sent: Monday, March 4, 2024 11:54 PM
> > To: Jamin Lin <jamin_lin@aspeedtech.com>; Peter Maydell
> > <peter.maydell@linaro.org>; Andrew Jeffery <andrew@codeconstruct.com.au>;
> > Joel Stanley <joel@jms.id.au>; Alistair Francis <alistair@alistair23.me>; open
> > list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> > <qemu-devel@nongnu.org>
> > Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> > <yunlin.tang@aspeedtech.com>
> > Subject: Re: [PATCH v2 0/9] Add AST2700 support
> >
> > Hello Jamin,
> >
> > On 3/4/24 10:29, Jamin Lin wrote:
> > > Changes from v1:
> > > The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700
> > SoC.
> > > Changes from v2:
> > > - replace is_aarch64 with is_bus64bit for sdmc patch review.
> > > - fix incorrect dram size for AST2700
> > >
> > > Test steps:
> > > 1. Download openbmc image for AST2700 from
> > >      https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.00
> > https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.00/
> > >      ast2700-default-obmc.tar.gz
> > > 2. untar ast2700-default-obmc.tar.gz
> > >      ```
> > >      tar -xf ast2700-default-obmc.tar.gz
> > >      ```
> > > 3. Run and the contents of scripts as following IMGDIR=ast2700-default
> > > UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
> > > UBOOT_DTB_ADDR=$((0x400000000 + ${UBOOT_SIZE}))
> > >
> > > qemu-system-aarch64 -M ast2700-evb -nographic\
> > >    -device
> > loader,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin,force-raw=on\
> > >    -device
> > loader,addr=${UBOOT_DTB_ADDR},file=${IMGDIR}/u-boot.dtb,force-raw=on\
> > >    -device loader,addr=0x430000000,file=${IMGDIR}/bl31.bin,force-raw=on\
> > >    -device
> > loader,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin,force-raw=on\
> > >    -device loader,addr=0x430000000,cpu-num=0\
> > >    -device loader,addr=0x430000000,cpu-num=1\
> > >    -device loader,addr=0x430000000,cpu-num=2\
> > >    -device loader,addr=0x430000000,cpu-num=3\
> > >    -smp 4\
> > >    -drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
> > >    -serial mon:stdio\
> > >    -snapshot
> > >
> > > Known Issue:
> > > 1. QEMU supports ARM Generic Interrupt Controller, version 3(GICv3)
> > > but not support Shared Peripheral Interrupt (SPI), yet.
> > > Added work around in INTC patch to set GICINT132[18] which was BMC
> > > UART interrupt if it received GICINT132, so users are able to type any
> > > key from keyboard to trigger GICINT132 interrupt until AST2700 boot
> > > into login prompt. It is a temporary solution.
> > > If users encounter boot stck and no booting log, please type any key
> > > from keyboard.
> >
> > I haven't looked at the GIC issue but I started reviewing what I received.
> >
> > The mailer issue needs to be fixed before we consider this patches for merge.
> > May be use an external email while keeping the same
> > From: and Signed-off-by address.
> Understand.
> Thanks for your suggestion. I am asking our IT help to fix our smtp server 
> issue.
> They are fixing it. I will use my external account to send V3 patch series if
> this issues does not be fixed, yet.
> > When you resend, could you please add an avocado test ?
> Sure, will create a patch for avocado test.

Forgot to add,

please update the documentation docs/system/arm/aspeed.rst.

Thanks,

C.