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Re: [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
From: |
Peter Maydell |
Subject: |
Re: [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling |
Date: |
Sat, 2 Mar 2024 10:59:19 +0000 |
On Fri, 1 Mar 2024 at 21:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/1/24 08:32, Peter Maydell wrote:
> > +static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
> > +{
> > + if ((env->cp15.scr_el3 & SCR_ECVEN) &&
> > + FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
> > + arm_is_el2_enabled(env) &&
> > + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H |
> > HCR_TGE)) {
>
> arm_hcr_el2_eff checks arm_is_el2_enabled and returns 0 if disabled.
Yes, and if it returns 0 then the E2H|TGE bits will not be E2H|TGE,
and so we'll incorrectly apply the CNTPOFF value. We can only elide
the arm_is_el2_enabled() test if we're checking for some HCR bit
being 1. (I also initially thought the arm_is_el2_enabled() check was
redundant and then found it was not :-))
-- PMM
- [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written, (continued)
- [PATCH 4/8] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written, Peter Maydell, 2024/03/01
- [PATCH 6/8] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0, Peter Maydell, 2024/03/01
- [PATCH 2/8] target/arm: Timer _EL02 registers UNDEF for E2H == 0, Peter Maydell, 2024/03/01
- [PATCH 5/8] target/arm: Implement new FEAT_ECV trap bits, Peter Maydell, 2024/03/01
- [PATCH 7/8] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling, Peter Maydell, 2024/03/01