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[PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64
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From: |
Richard Henderson |
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Subject: |
[PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64 |
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Date: |
Fri, 1 Mar 2024 19:15:41 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 3 +++
target/sparc/insns.decode | 2 ++
2 files changed, 5 insertions(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 4876d46ebb..9af30d8fa7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4905,6 +4905,9 @@ TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd)
TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
TRANS(FNADDd, VIS3, do_ddd, a, gen_op_fnaddd)
+TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
+TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
+
static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv_i64, TCGv_i64))
{
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index bc5640aa5f..c9dab4236d 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -441,10 +441,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....
\
FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r
FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d
FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r
+ FPADD64 10 ..... 110110 ..... 0 0100 0010 ..... @d_d_d
FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d
FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r
FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d
FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
+ FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d
FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r
--
2.34.1
- [PATCH 13/41] target/sparc: Add feature bits for VIS 3, (continued)
- [PATCH 13/41] target/sparc: Add feature bits for VIS 3, Richard Henderson, 2024/03/02
- [PATCH 14/41] target/sparc: Implement ADDXC, ADDXCcc, Richard Henderson, 2024/03/02
- [PATCH 15/41] target/sparc: Implement CMASK instructions, Richard Henderson, 2024/03/02
- [PATCH 16/41] target/sparc: Implement FCHKSM16, Richard Henderson, 2024/03/02
- [PATCH 17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, Richard Henderson, 2024/03/02
- [PATCH 11/41] target/sparc: Use gvec for VIS1 parallel add/sub, Richard Henderson, 2024/03/02
- [PATCH 18/41] target/sparc: Implement FNMUL, Richard Henderson, 2024/03/02
- [PATCH 19/41] target/sparc: Implement FLCMP, Richard Henderson, 2024/03/02
- [PATCH 20/41] target/sparc: Implement FMEAN16, Richard Henderson, 2024/03/02
- [PATCH 22/41] target/sparc: Implement FPADDS, FPSUBS, Richard Henderson, 2024/03/02
- [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64,
Richard Henderson <=
- [PATCH 23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8, Richard Henderson, 2024/03/02
- [PATCH 25/41] target/sparc: Implement LDXEFSR, Richard Henderson, 2024/03/02
- [PATCH 24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS, Richard Henderson, 2024/03/02
- [PATCH 26/41] target/sparc: Implement LZCNT, Richard Henderson, 2024/03/02
- [PATCH 27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd, Richard Henderson, 2024/03/02
- [PATCH 28/41] target/sparc: Implement PDISTN, Richard Henderson, 2024/03/02
- [PATCH 29/41] target/sparc: Implement UMULXHI, Richard Henderson, 2024/03/02
- [PATCH 31/41] target/sparc: Enable VIS3 feature bit, Richard Henderson, 2024/03/02
- [PATCH 30/41] target/sparc: Implement XMULX, Richard Henderson, 2024/03/02
- [PATCH 33/41] target/sparc: Add feature bit for VIS4, Richard Henderson, 2024/03/02