[PATCH 13/41] target/sparc: Add feature bits for VIS 3

[Richard Henderson]

The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus.  For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c       | 4 ++++
 target/sparc/cpu-feature.h.inc | 1 +
 2 files changed, 5 insertions(+)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 1178fca9e3..0ebb9c3aa9 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2145,6 +2145,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_HYPV(C)    ((C)->def->features & CPU_FEATURE_HYPV)
 # define avail_VIS1(C)    ((C)->def->features & CPU_FEATURE_VIS1)
 # define avail_VIS2(C)    ((C)->def->features & CPU_FEATURE_VIS2)
+# define avail_VIS3(C)    ((C)->def->features & CPU_FEATURE_VIS3)
+# define avail_VIS3B(C)   avail_VIS3(C)
 #else
 # define avail_32(C)      true
 # define avail_ASR17(C)   ((C)->def->features & CPU_FEATURE_ASR17)
@@ -2158,6 +2160,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
 # define avail_HYPV(C)    false
 # define avail_VIS1(C)    false
 # define avail_VIS2(C)    false
+# define avail_VIS3(C)    false
+# define avail_VIS3B(C)   false
 #endif
 
 /* Default case for non jump instructions. */
diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index a30b9255b2..3913fb4a54 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -13,3 +13,4 @@ FEATURE(CACHE_CTRL)
 FEATURE(POWERDOWN)
 FEATURE(CASA)
 FEATURE(FMAF)
+FEATURE(VIS3)
-- 
2.34.1