Re: [PATCH] Fix unexpected Illegal instruction error on RISC-V.

[Philippe Mathieu-Daudé]

Hi SiHuaN,

On 1/3/24 15:55, SiHuaN wrote:
> Avoid right-shifting by a negative number of bits when lmul is 8.

FYI Demin posted a similar patch, see:
https://lore.kernel.org/qemu-devel/20240225174114.5298-1-demin.han@starfivetech.com/

> Signed-off-by: SiHuaN <liyongtai@iscas.ac.cn>
> ---
>   target/riscv/vector_helper.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 84cec73eb2..f0158ea237 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, 
> target_ulong s1,
>            * VLEN * LMUL >= SEW
>            * VLEN >> (8 - lmul) >= sew
>            * (vlenb << 3) >> (8 - lmul) >= sew
> +         * Considering that lmul may be 8, the following form cannot be used.
>            * vlenb >> (8 - 3 - lmul) >= sew
>            */
>           if (vlmul == 4 ||
> -            cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> +            (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) {
>               vill = true;
>           }
>       }