Re: [PULL 2/2] aspeed: fix hardcode boot address 0

[Philippe Mathieu-Daudé]

Hi Jamin,

On 27/2/24 13:52, Cédric Le Goater wrote:
> From: Jamin Lin <jamin_lin@aspeedtech.com>
>
> In the previous design of ASPEED SOCs QEMU model, it set the boot
> address at "0" which was the hardcode setting for ast10x0, ast2600,
> ast2500 and ast2400.
>
> According to the design of ast2700, it has a bootmcu(riscv-32) which
> is used for executing SPL and initialize DRAM and copy u-boot image
> from SPI/Flash to DRAM at address 0x400000000 at SPL boot stage.
> Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
>
> Currently, qemu not support emulate two CPU architectures
> at the same machine. Therefore, qemu will only support
> to emulate CPU(cortex-a35) side for ast2700 and the boot
> address is "0x4 00000000".
>
> Fixed hardcode boot address "0" for future models using
> a different mapping address.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>

Tip for the email workflow: when someone provide a R-b tag for
a patch, please carry it on in your next iterations.

https://lore.kernel.org/qemu-devel/09f9ca34-4e0c-4ada-b808-643a8c578511@linaro.org/

See 
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#proper-use-of-reviewed-by-tags-can-aid-review

> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>   include/hw/arm/aspeed_soc.h | 2 --
>   hw/arm/aspeed.c             | 4 +++-
>   hw/arm/aspeed_ast2400.c     | 4 ++--
>   hw/arm/aspeed_ast2600.c     | 2 +-
>   4 files changed, 6 insertions(+), 6 deletions(-)